Datasheet LT1787, LT1787HV (Analog Devices) - 9

LT1787/LT1787HV
U U U PIN FUNCTIONS FIL–, FIL+ (Pins 1, 8):
Negative and Positive Filter Termi- where: nals. Differential mode noise can be filtered by connecting V + – OUT > VBIAS for VS > VS a capacitor across FIL– and FIL+. Pole frequency V + – OUT < VBIAS for VS < VS f–3dB = 1/(2πRC), R = 1.25kΩ. VOUT(O) is the no load output voltage at VSENSE = 0V.
V – S (Pin 2):
Negative Input Sense Terminal. Negative sense voltage will result in an output sinking current
VBIAS (Pin 6):
Output Bias Pin. For single supply, bidirec- proportional to the sense current. V – tional current sensing operation, V S is connected to an BIAS is connected to an internal gain-setting resistor R external bias voltage, so that at V G1A and supplies bias cur- SENSE = 0V, VOUT = rent to the internal amplifier. VOUT(O) + VBIAS. For dual supply, bidirectional current sensing operation, VBIAS is connected to ground. Thus,
DNC (Pin 3):
Do Not Connect. Connected internally. Do not VOUT = VOUT(O) at VSENSE = 0V. connect external circuitry to this pin.
V + S (Pin 7):
Positive Input Sense Terminal. Positive sense
VEE (Pin 4):
Negative Supply or Ground for Single Supply voltage will result in an output sourcing current propor- Operation. tional to the sense current. V + S is connected to an internal
V
gain-setting resistor R + and
OUT (Pin 5):
Voltage Output or Current Output propor- G2A. Connecting a supply to VS tional to the magnitude of the sense current flowing a load to V – S will allow the LT1787 to measure its own through R supply current. SENSE. For bidirectional current sensing opera- tion, VOUT = AV • VSENSE + VOUT(O) + VBIAS,
W BLOCK DIAGRAM
RSENSE ISENSE V – + S VS RG1A RG2A 1.25k 1.25k FIL– FIL+ R R G1B G2B 1.25k 1.25k – + A1 IOUT VBIAS ROUT Q1 Q2 20k VOUT VEE CURRENT MIRROR 1787 F 01
Figure 1. LT1787 Functional Diagram
1787fc 9