Datasheet LTC4150 (Analog Devices) - 9

LTC4150
APPLICATIONS INFORMATION INT, POL and CLR Interfacing to INT, POL, CLR and SHDN
INT asserts low each time the LTC4150 measures a unit The LTC4150 operates directly from the battery, while in of charge. At the same time, POL is latched to indicate most cases the microcontroller supply comes from some the polarity of the charge unit. The integrator and counter separate, regulated source. This poses no problem for INT continue running, so the microcontroller must service and and POL because they are open-drain outputs and can clear the interrupt before another unit of charge accumu- be pulled up to any voltage 9V or less, regardless of the lates. Otherwise, one measurement will be lost. The time voltage applied to the LTC4150’s VDD. available between interrupts is the reciprocal of CLR and SHDN inputs require special attention. To drive Equation 2: them, the microcontroller or external logic must generate a minimum logic high level of 1.9V. The maximum input 1 Time per INT Assertion = (9) level for these pins is VDD + 0.3V. If the microcontroller’s G VF •⏐VSENSE⏐ supply is more than this, resistive dividers must be used on CLR and SHDN. The schematic in Figure 6 shows an At 50mV full scale, the minimum time available is 596ms. application with INT driving CLR and microcontroller VCC To be conservative and accommodate for small, unex- > VDD. The resistive dividers on CLR and SHDN keep the pected excursions above the 50mV sense voltage limit, the voltages at these pins within the LTC4150’s VDD range. microcontroller should process the interrupt and polarity Choose R2 and R1 so that: information and clear INT within 500ms. (R1 + R2) ≥ 50RL (12) Toggling CLR low for at least 20μs resets INT high and unlatches POL. Since the LTC4150’s integrator and counter 1 R 1 9 . V ≤ V ≤ V ( ) Minimum CC DD (13) operate independently of the INT and POL latches, no 1 R + 2 R charge information is lost during the latched period or Equation 13 also applies to the selection of R3 and R4. while CLR is low. Charge/discharge information contin- The minimum V ues to accumulate during those intervals and accuracy DD is the lowest supply to the LTC4150 when the battery powering it is at its lowest discharged is unaffected. voltage. Once cleared, INT idles in a high state and POL indicates When the battery is removed in any application, the CLR real-time polarity of the battery current. POL high indicates and SHDN inputs are unpredictable. INT and POL outputs charge fl owing into the battery and low indicates charge may be erratic and should be ignored until after the bat- fl owing out. Indication of a polarity change requires at tery is replaced. least: If desired, the simple logic of Figure 4 may be used to 2 tPOL = (10) derive separate charge and discharge pulse trains from G • 1024 • V VF ⏐ SENSE⏐ INT and POL. where VSENSE is the smallest sense voltage magnitude before and after the polarity change. INT CHARGE CLR Open-drain outputs POL and INT can sink IOL = 1.6mA at V LTC4150 OL = 0.5V. The minimum pull-up resistance for these pins should be: DISCHARGE POL RL > (VCC – 0.5)/1.6mA (11) 4150 F04 where VCC is the logic supply voltage. Because speed isn’t
Figure 4. Unravelling Polarity—
an issue, pull-up resistors of 10k or higher are adequate.
Separate Charge and Discharge Outputs
4150fc 9 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM TIMING DIAGRAMS OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS