Datasheet LT1011, LT1011A (Analog Devices) - 10

LT1011/LT1011A
applicaTions inForMaTion
The input resistors should limit fault current to a reasonable 15V 5V value (0.1mA to 20mA). Power dissipation in the resis- 3 – 8 RL tors must be considered for continuous faults, especially 7 LT1011 OUTPUT when the LT1011 supplies are off. One final caution: lightly 2 + 1 loaded supplies may be forced to higher voltages by large 6 4 fault currents flowing through D1-D4. TTL OR CMOS DRIVE –15 (5V SUPPLY) R3 and R4 limit input current to the LT1011 to less than 3k 1mA when the input signals are held below V–. They may be eliminated if R1 and R2 are large enough to limit fault 1011 F04 current to less than 1mA.
Figure 4. Typical Strobe Circuit Input Slew Rate Limitations
level inputs. A 1pF capacitor between the output and Pin The response time of a comparator is typically measured 5 will greatly reduce oscillation problems without reduc- with a 100mV step and a 5mV to 10mV overdrive. Unfor- ing strobe speed. tunately, this does not simulate many real world situations DC hysteresis can also be added by placing a resistor where the step size is typically much larger and overdrive from the output to Pin 5. See step 5 under “Preventing can be significantly less. In the case of the LT1011, step Oscillation Problems.” size is important because the slew rate of internal nodes The pin (6) used for strobing is also one of the offset adjust will limit response time for input step sizes larger than pins. Current flow into or out of Pin 6 must be kept very 1V. At 5V step size, for instance, response time increases low (<0.2µA) when not strobing to prevent input offset from 150ns to 360ns. See the curve “Response Time vs voltage shifts. Input Step Size for more detail. If response time is critical and large input signals are ex-
Output Transistor
pected, clamp diodes across the inputs are recommended. The LT1011 output transistor is truly floating in the sense The slew rate limitation can also affect performance when that no current flows into or out of either the collector differential input voltage is low, but both inputs must or emitter when the transistor is in the “off” state. The slew quickly. Maximum suggested common mode slew equivalent circuit is shown in Figure 5. rate is 10V/µs. V+
Strobing
The LT1011 can be strobed by pulling current out of the I1 0.5mA STROBE pin. The output transistor is forced to an “off” state, giving a “hi” output at the collector (Pin 7). Currents as low as 250µA will cause strobing, but at low strobe D1 D2 COLLECTOR currents, strobe delay will be 200ns to 300ns. If strobe (OUTPUT) Q1 current is increased to 3mA, strobe delay drops to about 60ns. The voltage at the STROBE pin is about 150mV below R1 170Ω OUTPUT V+ at zero strobe current and about 2V below V+ for 3mA Q2 V– TRANSISTOR R2 strobe current. Do not ground the STROBE pin. It must 470Ω EMITTER be current driven. Figure 4 shows a typical strobe circuit. (GND PIN) 1011 F05 Note that there is no bypass capacitor between Pins 5 and
Figure 5. Output Transistor Circuitry
6. This maximizes strobe speed, but leaves the compara- tor more sensitive to oscillation problems for slow, low 1011afe 10 For more information www.linear.com/LT1011 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Applications Information Typical Applications Schematic Diagram Package Description Revision History Typical Application Related Parts