Datasheet LT1671 (Analog Devices) - 7

制造商Analog Devices
描述60ns, Low Power, Single Supply, Ground-Sensing Comparator
页数 / 页12 / 7 — APPLICATIONS INFORMATION. Common Mode Considerations. Input Bias Current. …
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APPLICATIONS INFORMATION. Common Mode Considerations. Input Bias Current. LATCH Pin Dynamics. Measuring Response Time

APPLICATIONS INFORMATION Common Mode Considerations Input Bias Current LATCH Pin Dynamics Measuring Response Time

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LT1671
U U W U APPLICATIONS INFORMATION Common Mode Considerations Input Bias Current
The LT1671 is specified for a common mode range of – 5V Input bias current is measured with the output held at to 3.5V on a ±5V supply or a common mode range of 0V 1.4V. As with any PNP differential input stage, the LT1671 to 3.5V on a single 5V supply. A more general consider- bias current flows out of the device. It will go to zero on an ation is that the common mode range is 0V below the input which is high and double on an input which is low. negative supply and 1.5V below the positive supply, inde- pendent of the actual supply voltage. The criterion for
LATCH Pin Dynamics
common mode limit is that the output still responds The LATCH pin is intended to retain input data (output correctly to a small differential input signal. latched) when the LATCH pin goes high. The pin will float When either input signal falls below the negative common to a high state when disconnected, so a flow-through mode limit, the internal PN diode formed with the sub- condition requires that the LATCH pin be grounded. The strate can turn on, resulting in significant current flow LATCH pin is designed to be driven with either a TTL or through the die. An external Schottky clamp diode CMOS output. It has no built-in hysteresis. between the input and the negative rail can speed up To guarantee data retention, the input signal must remain recovery from negative overdrive by preventing the sub- valid at least 35ns after the latch goes high (hold time), and strate diode from turning on. must be valid at least – 15ns before the latch goes high The zero crossing detector in Figure 1 demonstrates the (setup time). The negative setup time simply means that use of a fast clamp diode. The zero crossing detector the data arriving 15ns after (rather than before) the latch terminates the transmission line at its 50Ω characteristic signal is valid. When the latch signal goes low, new data impedance. Negative inputs should not fall below –2V to will appear at the output in approximately 60ns (latch keep the signal current within the clamp diode’s maximum propagation delay). forward rating. Positive inputs should not exceed the devices absolute maximum ratings nor the power rating
Measuring Response Time
on the terminating resistor. To properly measure the response of the LT1671 requires an input signal source with very fast rise times and 5V R exceptionally clean settling characteristics. The last S CABLE 50Ω requirement comes about because the standard compara- VIN + Q R tor test calls for an input step size that is large compared T 1N5712 LT1671 50Ω – to the overdrive amplitude. Typical test conditions are Q 100mV step size with 5mV overdrive. This requires an input signal that settles to within 1% (1mV) of final value 1671 F01 in only a few nanoseconds with no ringing or settling tail.
Figure 1. Fast Zero Crossing Detector
Ordinary high speed pulse generators are not capable of generating such a signal, and in any case, no ordinary Either input may go above the positive common mode oscilloscope is capable of displaying the waveform to limit without damaging the comparator. The upper voltage check its fidelity. Some means must be used to inherently limit is determined by an internal diode from each input to generate a fast, clean edge with known final value. The the positive supply. The input may go above the positive circuit shown in Figure 2 is the best electronic means of supply as long as it does not go far enough above it to generating a fast, clean step to test comparators. It uses conduct more than 10mA. Functionality will continue if the a very fast transistor in a common base configuration. The remaining input stays within the allowed common mode transistor is switched off with a fast edge from the genera- range. There will, however, be an increase in propagation tor and the collector voltage settles to exactly 0V in just a delay as the input signal switches back into the common few nanoseconds. The most important feature of this mode range. 7