Datasheet LT1711, LT1712 (Analog Devices) - 8

LT1711/LT1712
U U W U APPLICATIO S I FOR ATIO
latch when a flow-through condition is desired. The latch termination impedances (typically 100Ω to 400Ω) to pin is designed to be driven with either a TTL or CMOS eliminate any reflections that may occur. Also keep source output. It has built-in hysteresis of approximately 100mV, impedances as low as possible, preferably much less than so that slow moving or noisy input signals do not impact 1kΩ. latch performance. The input and output traces should also be isolated from For the LT1712, if only one of the comparators is being one another. Power supply traces can be used to achieve used at a given time, it is best to latch the second compara- this isolation as shown in Figure 1, a typical topside layout tor to avoid any possibility of interactions between the two of the LT1712 on a multilayer PC board. Shown is the comparators in the same package. topside metal etch including traces, pin escape vias and the land pads for a GN16 LT1712 and its adjacent X7R
High Speed Design Techniques
0805 bypass capacitors. The V+, V– and GND traces all The extremely fast speed of the LT1711/LT1712 necessi- shield the inputs from the outputs. Although the two V– tates careful attention to proper PC board layout and pins are connected internally, they should be shorted circuit design in order to prevent oscillations, as with together externally as well in order for both to function as most high speed comparators. The most common prob- shields. The same is true for the two V+ pins. The two GND lem involves power supply bypassing which is necessary pins are not connected internally, but in most applications to maintain low supply impedance. Resistance and induc- they are both connected directly to the ground plane. tance in supply wires and PC traces can quickly build up to unacceptable levels, thereby allowing the supply volt- ages to move as the supply current changes. This move- ment of the supply voltages will often result in improper operation. In addition, adjacent devices connected through an unbypassed supply can interact with each other through the finite supply impedances. Bypass capacitors furnish a simple solution to this prob- lem by providing a local reservoir of energy at the device, thus keeping supply impedance low. Bypass capacitors should be as close as possible to the LT1711/LT1712 171112 F01 supply pins. A good high frequency capacitor, such as a
Figure 1. Typical LT1712 Topside Metal
1000pF ceramic, is recommended in parallel with larger
for Multilayer PCB Layout
capacitors, such as a 0.1µF ceramic and a 4.7µF tantalum
Hysteresis
in parallel. These bypass capacitors should be soldered to Another important technique to avoid oscillations is to the output ground plane such that the return currents do provide positive feedback, also known as hysteresis, not pass through the ground plane under the input cir- from the output to the input. Increased levels of hyster- cuitry. The common tie point for these two ground planes esis, however, reduce the sensitivity of the device to input should be at the board ground connection. Such star- voltage levels, so the amount of positive feedback should grounding and ground plane separation is extremely im- be tailored to particular system requirements. The portant for the proper operation of ultra high speed circuits. LT1711/LT1712 are completely flexible regarding the Poor trace routes and high source impedances are also application of hysteresis, due to rail-to-rail inputs and the common sources of problems. Keep trace lengths as short complementary outputs. Specifically, feedback resistors as possible and avoid running any output trace adjacent can be connected from one of the outputs to its corre- to an input trace to prevent unnecessary coupling. If sponding input without regard to common mode consid- output traces are longer than a few inches, provide proper erations. Figure 2 shows several configurations. 8