Datasheet LT1713, LT1714 (Analog Devices) - 8

LT1713/LT1714
U U W U APPLICATIO S I FOR ATIO Common Mode Considerations Latch Pin Dynamics
The LT1713/LT1714 are specified for a common mode The internal latches of the LT1713/LT1714 comparators range of – 5.1V to 5.1V on a ±5V supply, or a common retain the input data (output latched) when their respective mode range of – 0.1V to 5.1V on a single 5V supply. A more latch pin goes high. The latch pin will float to a low state general consideration is that the common mode range is when disconnected, but it is better to ground the latch from 100mV below the negative supply to 100mV above when a flow-through condition is desired. The latch pin is the positive supply, independent of the actual supply volt- designed to be driven with either a TTL or CMOS output. age. The criteria for common mode limit is that the output It has built-in hysteresis of approximately 100mV, so that still responds correctly to a small differential input signal. slow moving or noisy input signals do not impact latch performance. For the LT1714, if only one of the compara- When either input signal falls outside the common mode tors is being used at a given time, it is best to latch the limit, the internal PN diode formed with the substrate can second comparator to avoid any possibility of interactions turn on resulting in significant current flow through the between the two comparators in the same package. die. Schottky clamp diodes between the inputs and the supply rails speed up recovery from excessive overdrive
High Speed Design Techniques
conditions by preventing these substrate diodes from turning on. A substantial amount of design effort has made the LT1713/LT1714 relatively easy to use. As with most high
Input Bias Current
speed comparators, careful attention to PC board layout and design is important in order to prevent oscillations. Input bias current is measured with the outputs held at The most common problem involves power supply by- 2.5V with a 5V supply voltage. As with any rail-to-rail passing which is necessary to maintain low supply im- differential input stage, the LT1713/LT1714 bias current pedance. Resistance and inductance in supply wires and flows into or out of the device depending upon the com- PC traces can quickly build up to unacceptable levels, mon mode level. The input circuit consists of an NPN pair thereby allowing the supply voltages to move as the and a PNP pair. For inputs near the negative rail, the NPN supply current changes. This movement of the supply pair is inactive, and the input bias current flows out of the voltages will often result in improper operation. In addi- device; for inputs near the positive rail, the PNP pair is tion, adjacent devices connected through an unbypassed inactive, and these currents flow into the device. For inputs supply can interact with each other through the finite far enough away from the supply rails, the input bias supply impedances. current will be some combination of the NPN and PNP bias currents. As the differential input voltage increases, the Bypass capacitors furnish a simple solution to this prob- input current of each pair will increase for one of the inputs lem by providing a local reservoir of energy at the device, and decrease for the other input. Large differential input thus keeping supply impedance low. Bypass capacitors voltages result in different input currents as the input should be as close as possible to the LT1713/LT1714 stage enters various regions of operation. To reduce the supply pins. A good high frequency capacitor, such as a influence of these changing input currents on system 0.1µF ceramic, is recommended in parallel with a larger operation, use a low source resistance. capacitor, such as a 4.7µF tantalum. 8