Datasheet LT1720, LT1721 (Analog Devices) - 8

LT1720/LT1721
APPLICATIONS INFORMATION Input Voltage Considerations Input Protection
The LT1720/LT1721 are specifi ed for a common mode range The input stage is protected against damage from large of –100mV to 3.8V when used with a single 5V supply. In differential signals, up to and beyond a differential voltage general the common mode range is 100mV below ground equal to the supply voltage, limited only by the absolute to 1.2V below VCC. The criterion for this common mode maximum currents noted. External input protection cir- limit is that the output still responds correctly to a small cuitry is only needed if currents would otherwise exceed differential input signal. Also, if one input is within the these absolute maximums. The internal catch diodes can common mode limit, the other input signal can go outside conduct current up to these rated maximums without the common mode limits, up to the absolute maximum latchup, even when the supply voltage is at the absolute limits (a diode drop past either rail at 10mA input current) maximum rating. and the output will retain the correct polarity. The LT1720/LT1721 input stage has general purpose When either input signal falls below the negative common internal ESD protection for the human body model. For mode limit, the internal PN diode formed with the substrate use as a line receiver, additional external protection may can turn on, resulting in signifi cant current fl ow through be required. As with most integrated circuits, the level the die. An external Schottky clamp diode between the of immunity to ESD is much greater when residing on a input and the negative rail can speed up recovery from printed circuit board where the power supply decoupling negative overdrive by preventing the substrate diode from capacitance will limit the voltage rise caused by an ESD turning on. pulse. When both input signals are below the negative common
Unused Inputs
mode limit, phase reversal protection circuitry prevents false output inversion to at least –400mV common mode. The inputs of any unused compartor should be tied off in However, the offset and hysteresis in this mode will increase a way that defi nes the output logic state. The easiest way dramatically, to as much as 15mV each. The input bias to do this is to tie IN+ to VCC and IN– to GND. currents will also increase.
Input Bias Current
When both input signals are above the positive common mode limit, the input stage will become debiased and Input bias current is measured with both inputs held at 1V. the output polarity will be random. However, the internal As with any PNP differential input stage, the LT1720/LT1721 hysteresis will hold the output to a valid logic level, and bias current fl ows out of the device. With a differential because the biasing of each comparator is completely input voltage of even just 100mV or so, there will be zero independent, there will be no impact on any other com- bias current into the higher of the two inputs, while the parator. When at least one of the inputs returns to within current fl owing out of the lower input will be twice the the common mode limits, recovery from this state will measured bias current. With more than two diode drops take as long as 1μs. of differential input voltage, the LT1720/LT1721’s input protection circuitry activates, and current out of the lower The propagation delay does not increase signifi cantly when input will increase an additional 30% and there will be a driven with large differential voltages. However, with low small bias current into the higher of the two input pins, levels of overdrive, an apparent increase may be seen with of 4μA or less. See the Typical Performance curve “Input large source resistances due to an RC delay caused by the Current vs Differential Input Voltage.” 2pF typical input capacitance. 17201fc 8