Datasheet LTC6752, LTC6752-1, LTC6752-2, LTC6752-3, LTC6752-4 (Analog Devices) - 9

LTC6752/LTC6752-1/ LTC6752-2/LTC6752-3/ LTC6752-4
elecTrical characTerisTics (VCC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3 only). The
l
denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Latching/Adjustable Hysteresis Characteristics (LTC6752-2/LTC6752-3 Only)
VLE/HYST LE/HYST Pin Voltage Open Circuit l 1.05 1.25 1.45 V RHYST Resistance Looking Into LE/HYST LE/HYST Pin Voltage < Open Circuit Value l 15 20 25 kΩ VHYST_LARGE Modified Input Hysteresis Voltage (Note 2) VLE/HYST = 800mV 40 mV VIL_LE Latch Pin Voltage, Latch Guaranteed l 0.3 V VIH_LE Latch Pin Voltage, Hysteresis Disabled Output Not Latched l 1.7 V IIH_LE Latch Pin Current High VLE/HYST = 1.7V l 30 72 µA IIL_LE Latch Pin Current Low VLE/HYST = 0.3V l –70 –47 µA tSETUP Latch Setup Time (Note 10) –2 ns tHOLD Latch Hold Time (Note 10) 2 ns tPL Latch To Output Delay 7 ns
Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)
ISD_VCC Shutdown Mode Input Stage Supply Current VSHDN = 0.6V 500 650 µA l 750 µA ISD_VDD Shutdown Mode Output Stage Supply VSHDN = 0.6V, LTC6752-2 170 400 µA Current l 450 µA VSHDN = 0.6V, LTC6752-3 240 600 µA l 650 µA tSD Shutdown Time Output Hi-Z 80 ns VIH_SD Shutdown Pin Voltage High Part Guaranteed to Be Powered On l 1.3 V VIL_SD Shutdown Pin Voltage Low Part Guaranteed to Be Powered Off l 0.6 V tWAKEUP Wake-Up Time from Shutdown VOD = 100mV, Output Valid 100 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Both hysteresis and offset are measured by determining positive may cause permanent damage to the device. Exposure to any Absolute and negative trip points (input values needed to change the output in the Maximum Rating condition for extended periods may affect device opposite direction). Hysteresis is defined as the difference of the two trip reliability and lifetime. points and offset as the average of the two trip points.
Note 2:
Reverse biased ESD protection diodes exist on all input,
Note 7:
Guaranteed by CMRR test. shutdown, latching/hysteresis and output pins. If the voltage on these
Note 8:
Propagation delays are measured with a step size of 150mV. pins goes 300mV beyond either supply rail, the current should be limited to less than 10mA. This parameter is guaranteed to meet specification
Note 9:
Propagation delay skew is defined as the difference of the through design and/or characterization. It is not production tested. propagation delays for positive and negative steps for the LTC6752, LTC6752-1, LTC6752-2 and LTC6752-4, and the difference in propagation
Note 3:
A heat sink may be required to keep the junction temperature delays between the complementary outputs for the LTC6752-3. below the absolute maximum rating. This parameter is guaranteed to meet specified performance through design and/or characterization. It is not
Note 10:
Latch setup time is defined as the minimum time before the production tested. LE/HYST pin is asserted low for an input signal change to be acquired and held at the output. Latch hold time is defined as the minimum time before
Note 4:
The LTC6752I/LTC6752-1I/LTC6752-2I/LTC6752-3I/LTC6752-4I an input signal change for a high to low transition on the LE/HYST pin to are guaranteed to meet specified performance from –40°C to 85°C. The prevent the output from changing. See Figure 7 for a graphical definition of LTC6752H/LTC6752-1H/LTC6752-2H/LTC6752-3H/LTC6752-4H are these terms. guaranteed to meet specified performance from –40°C to 125°C.
Note 11:
Toggling is defined to be valid if the output swings as follows:
Note 5:
Total output supply voltage range is guaranteed by the PSRR_VDD from 10% of V test. Total input supply voltage range for the LTC6752-2, LTC6752-3 and DD - VEE to 90% of VDD - VEE for the LTC6752-2/ LTC6752-3/LTC6752-4, and from 10% of V LTC6752-4 is guaranteed by the PSRR_V CC - VEE to 90% of VCC - VEE CC test. For the LTC6752 and for the LTC6752/LTC6752-1. It is tested with a 1kΩ load to V LTC6752-1, the supply voltage range is guaranteed by the PSRR_V CM CC test. The LTC6752MP is guaranteed to meet specified performance from –55°C
Note 12:
The devices have effectively infinite gain when hysteresis is to 125°C. enabled. 6752fc For more information www.linear.com/LTC6752 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics DC Typical Performance Characteristics AC Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts