Datasheet MCP6441, MCP6442, MCP6444 (Microchip) - 6
| 制造商 | Microchip |
| 描述 | The MCP6441 device is a single nanopower operational amplifier (op amp), which has low quiescent current (450 nA, typical) and rail-to-rail input and output operation |
| 页数 / 页 | 46 / 6 — MCP6441/2/4. Note:. 1,000. 100. PSRR (VDD = 1.4V to 6.0V, VCM = VSS). ) B … |
| 文件格式/大小 | PDF / 2.3 Mb |
| 文件语言 | 英语 |
MCP6441/2/4. Note:. 1,000. 100. PSRR (VDD = 1.4V to 6.0V, VCM = VSS). ) B d. (nV/Hz). RR,. CMRR (VDD = 6.0V, VCM = -0.3V to 6.3V)
该数据表的模型线
文件文字版本
MCP6441/2/4 Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 MΩ to VL and CL = 60 pF.
1,000 100 95 PSRR (VDD = 1.4V to 6.0V, VCM = VSS) 90 ) B d 85 ( 80 RR 75 PS (nV/Hz) 70 RR, 65 CMRR (VDD = 6.0V, VCM = -0.3V to 6.3V) CM 60 CMRR (VDD = 1.4V, VCM = -0.3V to 1.7V) Input Noise Voltage Density 55 100 50 0.1 1 10 100 1000 10000 0.1 1 10 100 1k 10k -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
CMRR, PSRR vs. Ambient vs. Frequency. Temperature.
350 1000 ts V 300 en DD = 6.0V rr u 250 t C 100 200 ffse ) O A Input Bias Current 150 d (p (nV/Hz) 100 f = 1 kHz 10 V ias an DD = 6.0 V 50 t B Input Noise Voltage Density pu Input Offset Current 0 In 1 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 25 45 65 85 105 125 Common Mode Input Voltage (V) Ambient Temperature (°C) FIGURE 2-8:
Input Noise Voltage Density
FIGURE 2-11:
Input Bias, Offset Current vs. Common Mode Input Voltage. vs. Ambient Temperature.
100 1000 90 PSRR- Representative Part ) TA = +125°C A ) p B 80 ( (d PSRR+ nt 100 R 70 R rre CMRR u T 60 A = +85°C PS C
c
50 ias RR, 10 t B CM 40 pu In V 30 DD = 6.0V 1 20 0 5 0 5 0 5 0 5 0 5 0 5 0 0.1 1 10 100 1000 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
Input Bias Current vs. Frequency. Common Mode Input Voltage. DS22257C-page 6 © 2010-2012 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 6.0V. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-11: Input Bias, Offset Current vs. Ambient Temperature. FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-13: Quiescent Current vs. Ambient Temperature. FIGURE 2-14: Quiescent Current vs. Power Supply Voltage. FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-16: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-21: Output Voltage Swing vs. Frequency. FIGURE 2-22: Output Voltage Headroom vs. Output Current. FIGURE 2-23: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-24: Slew Rate vs. Ambient Temperature. FIGURE 2-25: Small Signal Non-Inverting Pulse Response. FIGURE 2-26: Small Signal Inverting Pulse Response. FIGURE 2-27: Large Signal Non-Inverting Pulse Response. FIGURE 2-28: Large Signal Inverting Pulse Response. FIGURE 2-29: The MCP6441/2/4 Device Shows No Phase Reversal. FIGURE 2-30: Closed Loop Output Impedance vs. Frequency. FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-32: Channel-to-Channel Separation vs. Frequency (MCP6442/4 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 4.0 Application Information FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Protecting the Analog Inputs. FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. FIGURE 4-7: Battery Current Sensing. FIGURE 4-8: Precision Half-Wave Rectifier. FIGURE 4-9: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 MΩ to VL and CL = 60 pF.
1,000 100 95 PSRR (VDD = 1.4V to 6.0V, VCM = VSS) 90 ) B d 85 ( 80 RR 75 PS (nV/Hz) 70 RR, 65 CMRR (VDD = 6.0V, VCM = -0.3V to 6.3V) CM 60 CMRR (VDD = 1.4V, VCM = -0.3V to 1.7V) Input Noise Voltage Density 55 100 50 0.1 1 10 100 1000 10000 0.1 1 10 100 1k 10k -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
CMRR, PSRR vs. Ambient vs. Frequency. Temperature.
350 1000 ts V 300 en DD = 6.0V rr u 250 t C 100 200 ffse ) O A Input Bias Current 150 d (p (nV/Hz) 100 f = 1 kHz 10 V ias an DD = 6.0 V 50 t B Input Noise Voltage Density pu Input Offset Current 0 In 1 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 25 45 65 85 105 125 Common Mode Input Voltage (V) Ambient Temperature (°C) FIGURE 2-8:
Input Noise Voltage Density
FIGURE 2-11:
Input Bias, Offset Current vs. Common Mode Input Voltage. vs. Ambient Temperature.
100 1000 90 PSRR- Representative Part ) TA = +125°C A ) p B 80 ( (d PSRR+ nt 100 R 70 R rre CMRR u T 60 A = +85°C PS C
c
50 ias RR, 10 t B CM 40 pu In V 30 DD = 6.0V 1 20 0 5 0 5 0 5 0 5 0 5 0 5 0 0.1 1 10 100 1000 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
Input Bias Current vs. Frequency. Common Mode Input Voltage. DS22257C-page 6 © 2010-2012 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 6.0V. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-11: Input Bias, Offset Current vs. Ambient Temperature. FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-13: Quiescent Current vs. Ambient Temperature. FIGURE 2-14: Quiescent Current vs. Power Supply Voltage. FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-16: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-21: Output Voltage Swing vs. Frequency. FIGURE 2-22: Output Voltage Headroom vs. Output Current. FIGURE 2-23: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-24: Slew Rate vs. Ambient Temperature. FIGURE 2-25: Small Signal Non-Inverting Pulse Response. FIGURE 2-26: Small Signal Inverting Pulse Response. FIGURE 2-27: Large Signal Non-Inverting Pulse Response. FIGURE 2-28: Large Signal Inverting Pulse Response. FIGURE 2-29: The MCP6441/2/4 Device Shows No Phase Reversal. FIGURE 2-30: Closed Loop Output Impedance vs. Frequency. FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-32: Channel-to-Channel Separation vs. Frequency (MCP6442/4 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 4.0 Application Information FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Protecting the Analog Inputs. FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. FIGURE 4-7: Battery Current Sensing. FIGURE 4-8: Precision Half-Wave Rectifier. FIGURE 4-9: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service