Datasheet MCP6041, MCP6042, MCP6043, MCP6044 (Microchip) - 9
| 制造商 | Microchip |
| 描述 | Оperational amplifier (op amp) has a gain bandwidth product of 14 kHz with a low typical operating current of 600 nA and an offset voltage that is less than 3 mV |
| 页数 / 页 | 40 / 9 — MCP6041/2/3/4. Note:. 1000. 5.0. VDD = 5.5V. V 4.5. RL = 50 kΩ. (m 4.0. … |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
MCP6041/2/3/4. Note:. 1000. 5.0. VDD = 5.5V. V 4.5. RL = 50 kΩ. (m 4.0. 100. V 3.5. adr. eadr. OL – VSS. 3.0. DD – VOH. 2.5. age. ltage. or 2.0. t V. 1.5. tpu. – V
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文件文字版本
MCP6041/2/3/4 Note:
Unless otherwise indicated, T A = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.
1000 5.0 ; ) , ) VDD = 5.5V m V V 4.5 o om RL = 50 kΩ o (m o (m 4.0 SS SS V 100 V 3.5 adr V eadr OL – VSS – e – H 3.0 H OL V OL V DD – VOH 2.5 age V ltage lt o or V or 2.0 OL – VSS V 10 o DD – VOH t V OH OH 1.5 t V V tpu – V – 1.0 tpu DD Ou V 0.5 Ou V DD 1 0.0 0.01 0.1 1 10 -50 -25 0 25 50 75 100 125 Output Current Magnitude (mA) Ambient Temperature (°C) FIGURE 2-25:
Output Voltage Headroom
FIGURE 2-28:
Output Voltage Headroom vs. Output Current Magnitude. vs. Ambient Temperature.
5.5 10 5.0 VDD = 5.5V e 4.5 VDD = 5.5V 4.0 ltag High-to-Low o /ms) ) 3.5 V P (V P- 3.0 ut tp V V ate 2.5 u g ( 1 DD = 1.4V R 2.0 Low-to-High O in m lew 1.5 u Sw S VDD = 1.4V m 1.0 0.5 Maxi 0.0 0.1 -50 -25 0 25 50 75 100 125 10 100 1k 10k Ambient Temperature (°C) 1.E+01 1.E+02 1.E+03 1.E+04 Frequency (Hz) FIGURE 2-26:
Slew Rate vs. Ambient
FIGURE 2-29:
Maximum Output Voltage Temperature. Swing vs. Frequency.
25 25 G = +1 V/V G = -1 V/V 20) R 20 L = 50 kΩ RL = 50 kΩ 15/div 15) 10V iv m 10/d 5(5 5V e 0 05 m ltag-5o -5e (ag -10ut V -10lto -15tp -15V -20Ou -20 -25 -25 0.0 0.1 0.2 0.3 T 0.4 ime 0.5 (100 0. µs 6 /div) 0.7 0.8 0.9 1.0 0.0 0.1 0.2 0.3 0.4 Time 0.5 (100 0. µs/ 6 div) 0.7 0.8 0.9 1.0 FIGURE 2-27:
Small Signal Non-inverting
FIGURE 2-30:
Small Signal Inverting Pulse Pulse Response. Response. 2001-2013 Microchip Technology Inc. DS21669D-page 9 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6043 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +25°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6041/2/3/4 family shows no phase reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6042 and MCP6044 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6043 only). FIGURE 2-33: Input Current vs. Input Voltage (below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6043 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.5 MCP6043 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High-Side Battery Current Sensor. FIGURE 4-8: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service
Unless otherwise indicated, T A = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.
1000 5.0 ; ) , ) VDD = 5.5V m V V 4.5 o om RL = 50 kΩ o (m o (m 4.0 SS SS V 100 V 3.5 adr V eadr OL – VSS – e – H 3.0 H OL V OL V DD – VOH 2.5 age V ltage lt o or V or 2.0 OL – VSS V 10 o DD – VOH t V OH OH 1.5 t V V tpu – V – 1.0 tpu DD Ou V 0.5 Ou V DD 1 0.0 0.01 0.1 1 10 -50 -25 0 25 50 75 100 125 Output Current Magnitude (mA) Ambient Temperature (°C) FIGURE 2-25:
Output Voltage Headroom
FIGURE 2-28:
Output Voltage Headroom vs. Output Current Magnitude. vs. Ambient Temperature.
5.5 10 5.0 VDD = 5.5V e 4.5 VDD = 5.5V 4.0 ltag High-to-Low o /ms) ) 3.5 V P (V P- 3.0 ut tp V V ate 2.5 u g ( 1 DD = 1.4V R 2.0 Low-to-High O in m lew 1.5 u Sw S VDD = 1.4V m 1.0 0.5 Maxi 0.0 0.1 -50 -25 0 25 50 75 100 125 10 100 1k 10k Ambient Temperature (°C) 1.E+01 1.E+02 1.E+03 1.E+04 Frequency (Hz) FIGURE 2-26:
Slew Rate vs. Ambient
FIGURE 2-29:
Maximum Output Voltage Temperature. Swing vs. Frequency.
25 25 G = +1 V/V G = -1 V/V 20) R 20 L = 50 kΩ RL = 50 kΩ 15/div 15) 10V iv m 10/d 5(5 5V e 0 05 m ltag-5o -5e (ag -10ut V -10lto -15tp -15V -20Ou -20 -25 -25 0.0 0.1 0.2 0.3 T 0.4 ime 0.5 (100 0. µs 6 /div) 0.7 0.8 0.9 1.0 0.0 0.1 0.2 0.3 0.4 Time 0.5 (100 0. µs/ 6 div) 0.7 0.8 0.9 1.0 FIGURE 2-27:
Small Signal Non-inverting
FIGURE 2-30:
Small Signal Inverting Pulse Pulse Response. Response. 2001-2013 Microchip Technology Inc. DS21669D-page 9 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6043 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +25°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6041/2/3/4 family shows no phase reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6042 and MCP6044 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6043 only). FIGURE 2-33: Input Current vs. Input Voltage (below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6043 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.5 MCP6043 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High-Side Battery Current Sensor. FIGURE 4-8: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service