Datasheet MCP6141, MCP6142, MCP6143, MCP6144 (Microchip) - 8

MCP6141/2/3/4 Note:
Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF, and CS is tied low.
500 6 ) VDD = 5.0V V 5 G = +11 V/V 450 e (µ es (V) g 4 ltag 400 V o DD = 1.4V 3 et V 350 ut Volta 2 VIN 300 1 put Offs t, Outp In VDD = 5.5V Inpu 0 VOUT 250 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -1 Output Voltage (V) 0 5 10 Time (5 ms 15 /div) 20 25 FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
The MCP6141/2/3/4 Family Output Voltage. Shows No Phase Reversal.
1,000 300 y f = 1 kHz nsit 250 VDD = 5.0V e ) 200 age Density age D Hz) lt Hz lt /
√
o /
√
150 V (nV (n 100 Noise V 50 Input Noise Vo Input 100 0 0 5 0 5 0 5 0 5 0 5 0 5 0.1 1 10 100 1000 .5 -0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-8:
Input Noise Voltage Density
FIGURE 2-11:
Input Noise Voltage Density vs. Frequency. vs. Common Mode Input Voltage.
100 100 PSRR– 90 PSRR+ 95 ) CMRR 80 B) PSRR (VCM = VSS) (dB 90 70 RR RR (d S 60 85 , CM 50 R RR, P R 80 S CMRR (VDD = 5.0V, CM 40 P VCM = -0.3V to +5.3V) 75 30 Referred to Input 20 70 1 10 100 1k 10k 1 10 100 1,000 10,000 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
CMRR, PSRR vs. Ambient Frequency. Temperature. DS21668D-page 8 © 2009 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6143 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6141/2/3/4 Family Shows No Phase Reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel to Channel Separation vs. Frequency (MCP6142 and MCP6144 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6143 only). FIGURE 2-33: Input Current vs. Input Voltage (Below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Internal Chip Select (CS) Hysteresis (MCP6143 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 CS Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Stability FIGURE 4-3: Noise Gain for Non-inverting Gain Configuration. FIGURE 4-4: Noise Gain for Inverting Gain Configuration. FIGURE 4-5: Examples of Unstable Circuits for the MCP6141/2/3/4 Family. FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-7: Recommended RISO Values for Capacitive Loads. 4.5 MCP6143 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-8: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-9: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-10: High Side Battery Current Sensor. FIGURE 4-11: Summing Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulation Tool 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information