Datasheet MCP6231, MCP6231R, MCP6231U, MCP6232, MCP62314 (Microchip) - 4

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MCP6231/1R/1U/2/4 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics:
Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2, V ≈ OUT VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions AC Response
Gain Bandwidth Product GBWP — 300 — kHz Phase Margin PM — 65 — ° G = +1 V/V Slew Rate SR — 0.15 — V/µs
Noise
Input Noise Voltage Eni — 6.0 — µVP-P f = 0.1 Hz to 10 Hz Input Noise Voltage Density eni — 52 — nV/√Hz f = 1 kHz Input Noise Current Density ini — 0.6 — fA/√Hz f = 1 kHz
TEMPERATURE CHARACTERISTICS Electrical Characteristics:
Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions Temperature Ranges
Extended Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C
Note
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC70 θJA — 331 — °C/W Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W Thermal Resistance, 8L-DFN θJA — 84.5 — °C/W Thermal Resistance, 8L-MSOP θJA — 206 — °C/W Thermal Resistance, 8L-TDFN θJA — 41 — °C/W Thermal Resistance, 8L-PDIP θJA — 85 — °C/W Thermal Resistance, 8L-SOIC θJA — 163 — °C/W Thermal Resistance, 14L-PDIP θJA — 70 — °C/W Thermal Resistance, 14L-SOIC θJA — 120 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Note:
The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
1.1 Test Circuits
The test circuits used for the DC and AC tests are VDD 1 µF V 0.1 µF shown in Figure 1-1 and Figure 1-1. The bypass DD/2 capacitors are laid out according to the rules discussed R V N OUT in
Section 4.6 “PCB Surface Leakage”
.
MCP623X
CL RL VDD 1 µF R V G RF V 0.1 µF IN IN VL R V N OUT
MCP623X FIGURE 1-2:
AC and DC Test Circuit for Most Inverting Gain Conditions. CL RL R V G RF DD/2 VL
FIGURE 1-1:
AC and DC Test Circuit for Most Non-Inverting Gain Conditions. DS21881E-page 4 © 2009 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: PSRR, CMRR vs. Frequency. FIGURE 2-3: Input Bias Current at +85°C. FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-6: Input Bias Current at +125°C. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: Input Offset Voltage vs. Output Voltage. FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. FIGURE 2-13: Slew Rate vs. Ambient Temperature. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-20: The MCP6231/1R/1U/2/4 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply (VSS and VDD) 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: The MCP6231/1R/1U/2/4 Show No Phase Reversal. FIGURE 4-2: Simplified Analog Input ESD Structures. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: Summing Amplifier Circuit. FIGURE 4-9: Effect of Parasitic Capacitance at the Input. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information