Datasheet MCP6H71, MCP6H72, MCP6H74 (Microchip) - 7

制造商Microchip
描述Microchip’s MCP6H71/2/4 family of operational amplifiers (op amps) has a wide supply voltage range of 3.5V to 12V and rail-to-rail output operation
页数 / 页44 / 7 — MCP6H71/2/4. 2.0. TYPICAL PERFORMANCE CURVES. Note:. 16%. 1000. 14%. 800 …
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MCP6H71/2/4. 2.0. TYPICAL PERFORMANCE CURVES. Note:. 16%. 1000. 14%. 800 Samples. 800. T = +125°C. 12%. (µV). 600. T = +85°C. 400. T = +25°C. 10%

MCP6H71/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: 16% 1000 14% 800 Samples 800 T = +125°C 12% (µV) 600 T = +85°C 400 T = +25°C 10%

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MCP6H71/2/4 2.0 TYPICAL PERFORMANCE CURVES Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T  A = +25°C, VDD = +3.5V to +12V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
16% 1000 14% 800 Samples 800 T = +125°C A 12% (µV) 600 T = +85°C A 400 T = +25°C A 10% T = -40°C ltage 200 A o 8% 0 6% -200 tage of Occurances n -400 4% t Offset V -600 V = 5V DD 2% Perce Inpu Representative Part -800 0% -1000 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Common Mode Input Voltage (V) Input Offset Voltage (mV) FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs. Common Mode Input Voltage.
50% 1000 45% 800 T = +125°C A 800 Samples 40% T = +85°C T = - 40°C to +125°C A A (µV) 600 T = +25°C A 35% 400 T = -40°C A 30% ltage 200 o 25% 0 20% -200 tage of Occurances 15% -400 t Offset V 10% V = 12V DD -600 Representative Part Percen 5% Inpu -800 0% -1000 -9 -6 -3 0 3 6 9 -24 -21 -18 -15 -12 12 15 18 21 24 -0.5 1.5 3.5 5.5 7.5 9.5 11.5 Input Offset Voltage Drift (µV/°C) Common Mode Input Voltage (V) FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5:
Input Offset Voltage vs. Common Mode Input Voltage.
1000 1000 800 T = +125°C A 800 T = +85°C (µV) 600 A Representative Part T = +25°C (µV) 600 A V = 12V 400 T = -40°C DD A 400 V = 5V ltage DD 200 o ltage 200 o V = 3.5V DD 0 0 -200 -200 -400 t Offset V -400 t Offset V -600 V = 3.5V DD -600 Inpu Representative Part -800 Inpu -800 -1000 -1000 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 12 14 Common Mode Input Voltage (V) Output Voltage (V) FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs. Common Mode Input Voltage. Output Voltage.  2012-2014 Microchip Technology Inc. DS20002325C-page 7 Document Outline Features Applications Design Aids Description Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-10: CMRR, PSRR vs. Frequency. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-13: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-14: Quiescent Current vs. Ambient Temperature. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-16: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6H72/4 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-22: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Output Voltage Swing vs. Frequency. FIGURE 2-24: Output Voltage Headroom vs. Output Current. FIGURE 2-25: Output Voltage Headroom vs. Output Current. FIGURE 2-26: Output Voltage Headroom vs. Output Current. FIGURE 2-27: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-30: Slew Rate vs. Ambient Temperature. FIGURE 2-31: Slew Rate vs. Ambient Temperature. FIGURE 2-32: Small Signal Non-Inverting Pulse Response. FIGURE 2-33: Small Signal Inverting Pulse Response. FIGURE 2-34: Large Signal Non-Inverting Pulse Response. FIGURE 2-35: Large Signal Inverting Pulse Response. FIGURE 2-36: The MCP6H71/2/4 Shows No Phase Reversal. FIGURE 2-37: Closed-Loop Output Impedance vs. Frequency. FIGURE 2-38: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: High-Side Current Sensing Using Difference Amplifier. FIGURE 4-9: Active Full-Wave Rectifier. FIGURE 4-10: Triangle Waves Generator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service