Datasheet MCP601, MCP601R, MCP602, MCP603, MCP604 (Microchip) - 3

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MCP601/1R/2/3/4 AC CHARACTERISTICS Electrical Specifications:
Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, CL = 50 pF, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions Frequency Response
Gain Bandwidth Product GBWP — 2.8 — MHz Phase Margin PM — 50 — ° G = +1 V/V Step Response Slew Rate SR — 2.3 — V/µs G = +1 V/V Settling Time (0.01%) tsettle — 4.5 — µs G = +1 V/V, 3.8V step
Noise
Input Noise Voltage Eni — 7 — µVP-P f = 0.1 Hz to 10 Hz Input Noise Voltage Density eni — 29 — nV/√Hz f = 1 kHz eni — 21 — nV/√Hz f = 10 kHz Input Noise Current Density ini — 0.6 — fA/√Hz f = 1 kHz
MCP603 CHIP SELECT (CS) CHARACTERISTICS Electrical Specifications:
Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, CL = 50 pF, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions CS Low Specifications
CS Logic Threshold, Low VIL VSS — 0.2 VDD V CS Input Current, Low ICSL -1.0 — — µA CS = 0.2VDD
CS High Specifications
CS Logic Threshold, High VIH 0.8 VDD — VDD V CS Input Current, High ICSH — 0.7 2.0 µA CS = VDD Shutdown VSS current IQ_SHDN -2.0 -0.7 — µA CS = VDD Amplifier Output Leakage in Shutdown IO_SHDN — 1 — nA
Timing
CS Low to Amplifier Output Turn-on Time tON — 3.1 10 µs CS ≤ 0.2VDD, G = +1 V/V CS High to Amplifier Output High-Z Time tOFF — 100 — ns CS ≥ 0.8VDD, G = +1 V/V, No load. Hysteresis VHYST — 0.4 — V VDD = 5.0V CS t t ON OFF VOUT Hi-Z Output Active Hi-Z 2 nA IDD (typical) 230 µA (typical) -230 µA ISS -700 nA (typical) (typical) 2 nA CS 700 nA (typical) Current (typical)
FIGURE 1-1:
MCP603 Chip Select (CS) Timing Diagram. © 2007 Microchip Technology Inc. DS21314G-page 3 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: MCP603 Chip Select (CS) Timing Diagram. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-2: Slew Rate vs. Temperature. FIGURE 2-3: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-4: Quiescent Current vs. Supply Voltage. FIGURE 2-5: Quiescent Current vs. Temperature. FIGURE 2-6: Input Noise Voltage Density vs. Frequency. FIGURE 2-7: Input Offset Voltage. FIGURE 2-8: Input Offset Voltage vs. Temperature. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.7V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: CMRR, PSRR vs. Temperature. FIGURE 2-12: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-13: Channel-to-Channel Separation vs. Frequency. FIGURE 2-14: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-15: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-16: CMRR, PSRR vs. Frequency. FIGURE 2-17: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Supply Voltage. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Load Resistance. FIGURE 2-20: Output Voltage Headroom vs. Output Current. FIGURE 2-21: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-22: DC Open-Loop Gain vs. Temperature. FIGURE 2-23: Output Voltage Headroom vs. Temperature. FIGURE 2-24: Output Short-Circuit Current vs. Supply Voltage. FIGURE 2-25: Large Signal Non-Inverting Pulse Response. FIGURE 2-26: Small Signal Non-Inverting Pulse Response. FIGURE 2-27: Chip Select Timing (MCP603). FIGURE 2-28: Large Signal Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Quiescent Current Through VSS vs. Chip Select Voltage (MCP603). FIGURE 2-31: Chip Select Pin Input Current vs. Chip Select Voltage. FIGURE 2-32: Hysteresis of Chip Select’s Internal Switch. FIGURE 2-33: The MCP601/1R/2/3/4 family of op amps shows no phase reversal under input overdrive. FIGURE 2-34: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table For Single Op Amps TABLE 3-2: Pin Function Table For Dual And Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range. 4.2 Rail-to-Rail Output 4.3 MCP603 Chip Select 4.4 Capacitive Loads FIGURE 4-4: Output resistor RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO values for capacitive loads. 4.5 Supply Bypass 4.6 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.7 PCB Surface Leakage FIGURE 4-7: Example Guard Ring layout. 4.8 Typical Applications FIGURE 4-8: Second-Order, Low-Pass Sallen-Key Filter. FIGURE 4-9: Second-Order, Low-Pass Multiple-Feedback Filter. FIGURE 4-10: Three-Op Amp Instrumentation Amplifier. FIGURE 4-11: Two-Op Amp Instrumentation Amplifier. FIGURE 4-12: Photovoltaic Mode Detector. FIGURE 4-13: Photoconductive Mode Detector. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulatior Tool 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information