Datasheet MCP6281, MCP6281R, MCP6282, MCP6283, MCP6284, MCP6285 (Microchip) - 9

MCP6281/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
5.0 5.0 G = +1V/V G = -1V/V 4.5 V 4.5 DD = 5.0V VDD = 5.0V 4.0 4.0 3.5 3.5 3.0 3.0 tage (V) 2.5 2.5 2.0 2.0 1.5 1.5 Output Vol Output Voltage (V) 1.0 1.0 0.5 0.5 0.0 0.0
0.E+00 2.E-06 4.E-06 6.E-06 8.E-06 1.E-05 1.E-05 1.E-05 2.E-05 2.E-05 2.E-05 0.E+00 2.E-06 4.E-06 6.E-06 8.E-06 1.E-05 1.E-05 1.E-05 2.E-05 2.E-05 2.E-05
Time (2 µs/div) Time (2 µs/div) FIGURE 2-25:
Large-Signal, Non-inverting
FIGURE 2-28:
Large-Signal, Inverting Pulse Response. Pulse Response.
G = +1V/V ) iv G = -1V/V /d ltage (10 mV o tput V u Output Voltage (10 mV/div) O Time (500 ns/div) Time (500 ns/div) FIGURE 2-26:
Small-Signal, Non-inverting
FIGURE 2-29:
Small-Signal, Inverting Pulse Response. Pulse Response.
6.0 2.5 V VDD = 5.5V DD = 2.2V 5.5 es G = +1V/V g G = +1V/V 5.0 CS Voltage ages V 2.0 lta CS Voltage V IN = VSS IN = VSS lt o 4.5 o V 4.0 ut V ut 1.5 3.5 p tp ) V u OUT (V V 3.0 (V) OUT Output On t, O 2.5 1.0 ct, Out 2.0 1.5 0.5 ip Selec ip Sele 1.0 h h Output High-Z Output On C C 0.5 Output High-Z 0.0
0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05
0.0
0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05 4.0E-05 4.5E-05 5.0E-05
Time (5 µs/div) Time (5 µs/div) FIGURE 2-27:
Chip Select (CS) to
FIGURE 2-30:
Chip Select (CS) to Amplifier Output Response Time at V Amplifier Output Response Time at V DD = 2.2V DD = 5.5V (MCP6283 and MCP6285 only). (MCP6283 and MCP6285 only). © 2008 Microchip Technology Inc. DS21811E-page 9 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6283 and MCP6285. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85 ˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.2V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125 ˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: CMRR, PSRR vs. Frequency. FIGURE 2-9: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +85˚C. FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +125˚C. FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Input Noise Voltage Density vs. Frequency. FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 2.2V (MCP6283 and MCP6285 only). FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 1 kHz. FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6282 and MCP6284 only). FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6283 and MCP6285 only). FIGURE 2-25: Large-Signal, Non-inverting Pulse Response. FIGURE 2-26: Small-Signal, Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time at VDD = 2.2V (MCP6283 and MCP6285 only). FIGURE 2-28: Large-Signal, Inverting Pulse Response. FIGURE 2-29: Small-Signal, Inverting Pulse Response. FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at VDD = 5.5V (MCP6283 and MCP6285 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-32: The MCP6281/1R/2/3/4/5 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6285’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input (CS) 3.5 Power Supply Pins 4.0 Application infoRmation 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP628X Chip Select (CS) 4.5 Cascaded Dual Op Amps (MCP6285) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Sallen-Key High-Pass Filter. FIGURE 4-9: Miller Integrator. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Buffered Non-inverting Integrator with Chip Select. FIGURE 4-14: Integrator Circuit with Active Compensation. FIGURE 4-15: Second-Order Multiple Feedback Low-Pass Filter with an Extra Pole-Zero Pair. FIGURE 4-16: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-17: Capacitorless Second-Order Low-Pass Filter with Chip Select. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information