Datasheet MCP660, MCP661, MCP662, MCP663, MCP664, MCP665, MCP669 (Microchip) - 5

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MCP660/1/2/3/4/5/9 DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics:
Unless indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL, CL = 20 pF and CS = VSS (refer to Figures 1-1 and 2-1).
Parameters Sym. Min. Typ. Max. Units Conditions CS Low Specifications
CS Logic Threshold, Low VIL VSS — 0.2VDD V CS Input Current, Low ICSL — -0.1 — nA CS = 0V
CS High Specifications
CS Logic Threshold, High VIH 0.8VDD — VDD V CS Input Current, High ICSH — -0.7 — µA CS = VDD GND Current I -2 -1 SS — µA CS Internal Pull-Down Resistor RPD — 5 — M Amplifier Output Leakage IO(LEAK) — 40 — nA CS = VDD, TA = +125°C
CS Dynamic Specifications
CS Input Hysteresis V — HYST 0.25 — V CS High to Amplifier Off Time tOFF — 200 — ns G = +1 V/V, VL = VSS (output goes High Z) CS = 0.8VDD to VOUT = 0.1(VDD/2) CS Low to Amplifier On Time tON — 2 10 µs G = + 1 V/V, VL = VSS CS = 0.2VDD to VOUT = 0.9(VDD/2)
TEMPERATURE SPECIFICATIONS Electrical Characteristics:
Unless otherwise indicated, all limits are specified for VDD = +2.5V to +5.5V, VSS = GND.
Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges
Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C
Note 1
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 201.0 — °C/W Thermal Resistance, 6L-SOT-23 θJA — 190.5 — °C/W Thermal Resistance, 8L-3x3 DFN θJA — 56.7 — °C/W
Note 2
Thermal Resistance, 8L-MSOP θJA — 211 — °C/W Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W Thermal Resistance, 8L-2x3 TDFN θJA — 52.5 — °C/W Thermal Resistance, 10L-3x3 DFN θJA — 54.0 — °C/W
Note 2
Thermal Resistance, 10L-MSOP θJA — 202 — °C/W Thermal Resistance, 14L-SOIC θJA — 90.8 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Thermal Resistance, 16L-QFN θJA — 52.1 — °C/W
Note 1:
Operation must not cause TJ to exceed the Maximum Junction Temperature specification (+150°C).
2:
Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.  2009-2014 Microchip Technology Inc. DS20002194E-page 5 Document Outline 60 MHz, 32 V/µs Rail-to-Rail Output (RRO) Op Amps Features: Typical Applications: Design Aids: Description: Typical Application Circuit High Gain-Bandwidth Op Amp Portfolio Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications DC Electrical Specifications AC Electrical Specifications Digital Electrical Specifications Temperature Specifications 1.3 Timing Diagram FIGURE 1-1: Timing Diagram. 1.4 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves 2.1 DC Signal Inputs FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Power Supply Voltage with VCM = 0V. FIGURE 2-4: Input Offset Voltage vs. Output Voltage. FIGURE 2-5: Low-Input Common-Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-6: High-Input Common-Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-7: Input Offset Voltage vs. Common-Mode Voltage with VDD = 2.5V. FIGURE 2-8: Input Offset Voltage vs. Common-Mode Voltage with VDD = 5.5V. FIGURE 2-9: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-10: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-11: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-13: Input Bias Current vs. Input Voltage (below VSS). FIGURE 2-14: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +85°C. FIGURE 2-15: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +125°C. 2.2 Other DC Voltages and Currents FIGURE 2-16: Output Voltage Headroom vs. Output Current. FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-18: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-19: Supply Current vs. Power Supply Voltage. FIGURE 2-20: Supply Current vs. Common-Mode Input Voltage. 2.3 Frequency Response FIGURE 2-21: CMRR and PSRR vs. Frequency. FIGURE 2-22: Open-Loop Gain vs. Frequency. FIGURE 2-23: Gain-Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-24: Gain-Bandwidth Product and Phase Margin vs. Common-Mode Input Voltage. FIGURE 2-25: Gain-Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-26: Closed-Loop Output Impedance vs. Frequency. FIGURE 2-27: Gain Peaking vs. Normalized Capacitive Load. FIGURE 2-28: Channel-to-Channel Separation vs. Frequency. 2.4 Noise and Distortion FIGURE 2-29: Input Noise Voltage Density vs. Frequency. FIGURE 2-30: Input Noise Voltage Density vs. Input Common-Mode Voltage with f = 100 Hz. FIGURE 2-31: Input Noise Voltage Density vs. Input Common-Mode Voltage with f = 1 MHz. FIGURE 2-32: Input Noise vs. Time with 0.1 Hz Filter. FIGURE 2-33: THD+N vs. Frequency. FIGURE 2-34: Change in Gain Magnitude and Phase vs. DC Input Voltage. 2.5 Time Response FIGURE 2-35: Non-Inverting Small Signal Step Response. FIGURE 2-36: Non-Inverting Large Signal Step Response. FIGURE 2-37: Inverting Small Signal Step Response. FIGURE 2-38: Inverting Large Signal Step Response. FIGURE 2-39: The MCP660/1/2/3/4/5/9 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-40: Slew Rate vs. Ambient Temperature. FIGURE 2-41: Maximum Output Voltage Swing vs. Frequency. 2.6 Chip Select Response FIGURE 2-42: CS Current vs. Power Supply Voltage. FIGURE 2-43: CS and Output Voltages vs. Time with VDD = 2.5V. FIGURE 2-44: CS and Output Voltages vs. Time with VDD = 5.5V. FIGURE 2-45: CS Hysteresis vs. Ambient Temperature. FIGURE 2-46: CS Turn-On Time vs. Ambient Temperature. FIGURE 2-47: CS’s Pull-Down Resistor (RPD) vs. Ambient Temperature. FIGURE 2-48: Quiescent Current in Shutdown vs. Power Supply Voltage. FIGURE 2-49: Output Leakage Current vs. Output Voltage. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Chip Select Digital Input (CS) 3.5 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity-Gain Voltage Limitations for Linear Operation. 4.2 Rail-to-Rail Output FIGURE 4-4: Output Current. FIGURE 4-5: Diagram for Power Calculations. 4.3 Distortion 4.4 Improving Stability FIGURE 4-6: Output Resistor, RISO, Stabilizes Large Capacitive Loads. FIGURE 4-7: Recommended RISO Values for Capacitive Loads. FIGURE 4-8: Amplifier with Parasitic Capacitance. FIGURE 4-9: Maximum Recommended RF vs. Gain. 4.5 MCP663 and MCP665 Chip Select 4.6 Power Supply 4.7 High Speed PCB Layout 4.8 Typical Applications FIGURE 4-10: 50W Line Driver. FIGURE 4-11: Transimpedance Amplifier for an Optical Detector. FIGURE 4-12: H-Bridge Driver. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Design and Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service