Datasheet AD4003, AD4007, AD4011 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 18-Bit, 500 kSPS, Easy Drive, Differential SAR ADC |
| 页数 / 页 | 38 / 8 — AD4003/AD4007/AD4011. Data Sheet. Table 3. Register Read/Write Timing … |
| 修订版 | C |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
AD4003/AD4007/AD4011. Data Sheet. Table 3. Register Read/Write Timing Parameter. Symbol. Min. Typ. Max. Unit. Y% VIO1. X% VIO1. tDELAY. V 2
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文件文字版本
AD4003/AD4007/AD4011 Data Sheet Table 3. Register Read/Write Timing Parameter Symbol Min Typ Max Unit
READ/WRITE OPERATION CNV Pulse Width1 tCNVH 10 ns SCK Period tSCK VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns SCK Low Time tSCKL 3 ns SCK High Time tSCKH 3 ns READ OPERATION CNV Low to SDO D17 MSB Valid Delay tEN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns SCK Falling Edge to Data Remains Valid tHSDO 1.5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO >2.7 V 7.5 ns VIO >1.7 V 10.5 ns CNV Rising Edge to SDO High Impedance tDIS 20 ns WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge tSSDISCK 2 ns SDI Valid Hold Time from SCK Rising Edge tHSDISCK 2 ns CNV Rising Edge to SCK Edge Hold Time tHCNVSCK 0 ns CNV Falling Edge to SCK Active Edge Setup Time tSCNVSCK 6 ns 1 For turbo mode, tCNVH must match the tQUIET1 minimum.
Y% VIO1 X% VIO1 tDELAY tDELAY V 2 IH V 2 IH 2 V 2 VIL IL 1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.
002
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 1.
14957- Figure 2. Voltage Levels for Timing
Table 4. Achievable Throughput for Different Modes of Operation Parameter Test Conditions/Comments Min Typ Max Unit
THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 2 MSPS 3-Wire and 4-Wire Turbo Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.78 MSPS 3-Wire and 4-Wire Mode fSCK = 100 MHz, VIO ≥ 2.7 V 1.75 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.62 MSPS 3-Wire and 4-Wire Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 1.59 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.44 MSPS Rev. A | Page 8 of 38 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Applications Information Typical Application Diagrams Analog Inputs Input Overvoltage Clamp Circuit Differential Input Considerations Switched Capacitor Input RC Filter Values Driver Amplifier Choice Single to Differential Driver High Frequency Input Signals Multiplexed Applications Ease of Drive Features Input Span Compression High-Z Mode Long Acquisition Phase Voltage Reference Input Power Supply Digital Interface Register Read/Write Functionality Status Word /CS Mode, 3-Wire Turbo Mode /CS Mode, 3-Wire Without Busy Indicator /CS Mode, 3-Wire with Busy Indicator /CS Mode, 4-Wire Turbo Mode /CS Mode, 4-Wire Without Busy Indicator /CS Mode, 4-Wire with Busy Indicator Daisy-Chain Mode Layout Guidelines Evaluating the AD4003/AD4007/AD4011 Performance Outline Dimensions Ordering Guide
READ/WRITE OPERATION CNV Pulse Width1 tCNVH 10 ns SCK Period tSCK VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns SCK Low Time tSCKL 3 ns SCK High Time tSCKH 3 ns READ OPERATION CNV Low to SDO D17 MSB Valid Delay tEN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns SCK Falling Edge to Data Remains Valid tHSDO 1.5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO >2.7 V 7.5 ns VIO >1.7 V 10.5 ns CNV Rising Edge to SDO High Impedance tDIS 20 ns WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge tSSDISCK 2 ns SDI Valid Hold Time from SCK Rising Edge tHSDISCK 2 ns CNV Rising Edge to SCK Edge Hold Time tHCNVSCK 0 ns CNV Falling Edge to SCK Active Edge Setup Time tSCNVSCK 6 ns 1 For turbo mode, tCNVH must match the tQUIET1 minimum.
Y% VIO1 X% VIO1 tDELAY tDELAY V 2 IH V 2 IH 2 V 2 VIL IL 1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.
002
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 1.
14957- Figure 2. Voltage Levels for Timing
Table 4. Achievable Throughput for Different Modes of Operation Parameter Test Conditions/Comments Min Typ Max Unit
THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 2 MSPS 3-Wire and 4-Wire Turbo Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.78 MSPS 3-Wire and 4-Wire Mode fSCK = 100 MHz, VIO ≥ 2.7 V 1.75 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.62 MSPS 3-Wire and 4-Wire Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 1.59 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.44 MSPS Rev. A | Page 8 of 38 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Applications Information Typical Application Diagrams Analog Inputs Input Overvoltage Clamp Circuit Differential Input Considerations Switched Capacitor Input RC Filter Values Driver Amplifier Choice Single to Differential Driver High Frequency Input Signals Multiplexed Applications Ease of Drive Features Input Span Compression High-Z Mode Long Acquisition Phase Voltage Reference Input Power Supply Digital Interface Register Read/Write Functionality Status Word /CS Mode, 3-Wire Turbo Mode /CS Mode, 3-Wire Without Busy Indicator /CS Mode, 3-Wire with Busy Indicator /CS Mode, 4-Wire Turbo Mode /CS Mode, 4-Wire Without Busy Indicator /CS Mode, 4-Wire with Busy Indicator Daisy-Chain Mode Layout Guidelines Evaluating the AD4003/AD4007/AD4011 Performance Outline Dimensions Ordering Guide