Datasheet AD8074, AD8075 (Analog Devices) - 9

AD8074/AD8075 THEORY OF OPERATION APPLICATIONS
The AD8074 (G = +1) and AD8075 (G = +2) are triple-channel,
Response Tuning
high-speed buffers with TTL-compatible output enable control. It has been mentioned in passing that the primary cause of over- Optimized for buffering RGB (red, green, blue) video sources, shoot for the AD8074 and AD8075 is the presence of large the devices have high peak slew rates, maintaining their band- reactive loads at the output. If the system exhibits excessive width for large signals. Additionally, the buffers are compensated ringing while settling, a 10 Ω–50 Ω series resistor may be used for high phase margin, minimizing overshoot for good pixel at the output to isolate the emitter-follower output buffer from resolution. The buffers also have video specifications that are the reactive load. If the output exhibits an overdamped response, suitable for buffering NTSC or PAL composite signals. the system designer may add a few pF shunt capacitance at the output to tune for a faster edge transition. A system with a small The buffers are organized as three independent channels, each degree of overshoot will settle faster than an overdamped system. with an input transconductance stage and an output trans- impedance stage. Each channel is characterized by low input
2.0
capacitance and high input impedance. The transconductance
RS = 10
⍀ stages, NPN differential pairs, source signal current into the folded
1.5 CL = 10pF
cascode output stages. Each output stage contains a compensat-
RS = 0
⍀
1.0
ing network and emitter follower output buffer. Internal voltage
CL = 5pF
feedback sets the gain, the AD8074 being configured as a unity
0.5
gain follower, and the AD8075 as a gain-of-two amplifier with a
RS = 20
⍀ feedback network. The architecture provides drive for a reverse-
0 CL = 15pF
terminated video load (150 Ω) with low differential gain and
–0.5
phase error for relatively low power consumption. Careful chip design and layout allow excellent crosstalk isolation between
–1.0 RS V
channels.
IN VOUT C –1.5 75 L 1k
⍀ ⍀ One logic pin, OE, controls whether the three outputs are
2ns
enabled, or disabled to a high-impedance state. The high imped-
–2.0
ance disable allows larger matrices to be built when busing the Figure 2. Driving Capacitive Loads outputs together. When disabled, the AD8074 and AD8075 con-
Single Supply Operation
sume a fifth the power as when enabled. In the case of the The AD8074 and AD8075 may be operated from a single 10 V AD8075 (G = +2), a feedback isolation scheme is used so that supply. In this configuration, the AD8075’s AGND pins must the impedance of the gain-of-two feedback network does not be tied near midsupply, as AGND provides the reference for the load the output. ground buffer, to which the internal gain network is terminated. Full power bandwidth for an undistorted sinusoid is often calcu- Logic is referenced to DGND. The buffers are disabled in single lated using peak slew rate from the equation: supply operation for VOE > VDGND + ~2.0 V and enabled for Peak Slew Rate VOE < VDGND + 0.8 V. TTL logic levels are expected. The fol- Full Power Bandwidth = lowing restrictions are placed upon the digital ground potential: 2 × π × Sinusoidal Amplitude ≤ ≤ Peak slew rate is not the same as average slew rate (25% to 3 5 . V VAVCC – VDGND 12 V 75%) which is typically specified. For a natural response, peak VDGND ≥ VAVEE slew rate may be 2.7 times larger than average slew rate. There- The architecture of the output buffer is such that the output fore, calculating a full power bandwidth with a specified average voltage can swing to within ~2.3 V of either rail. For example, if slew rate will give a pessimistic result. the output need swing only 2 V, then the buffers could be oper- The primary cause of overshoot in these amplifiers is the pres- ated on dual 3.5 V or single 7 V supplies. It is cautioned that ence of large reactive loads at the output and insufficient series saturation effects may become noticeable when the output swings isolation of the load. However, it is possible to overdrive these within 2.6 V of either rail. The system designer may opt to amplifiers with 1 V, subnanosecond input-pulse edges. The use this characteristic to his or her advantage by using the ensuing dynamics may give rise to subnanosecond overshoot. To soft-saturation regime, (2.2 V–2.6 V from the supply rails), to reduce these effects, an edge-rate limiting network at the input tame excessive overshoot. The designer is cautioned that a should be considered for input transition times less than 0.5 ns. charge storage associated time delay of several nanoseconds is incurred when recovering from soft-saturation. This effect results in longer settling tails. Rev. B –9– Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT DESCRIPTION AD8074/AD8075-SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ESD CAUTION MAXIMUM POWER DISSIPATION AD8074/AD8075-TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION OUTLINE DIMENSIONS ORDERING GUIDE