Datasheet LTC1090 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Single Chip 10-Bit Data Acquisition System |
| 页数 / 页 | 28 / 10 — APPLICATIO S I FOR ATIO. Multiplexer (MLIX) Address. Table 1. Multiplexer … |
| 文件格式/大小 | PDF / 356 Kb |
| 文件语言 | 英语 |
APPLICATIO S I FOR ATIO. Multiplexer (MLIX) Address. Table 1. Multiplexer Channel Selection. MUX ADDRESS
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LTC1090
U U W U APPLICATIO S I FOR ATIO
Data transfer is initiated by a falling chip select (CS) signal.
Multiplexer (MLIX) Address
After the falling CS is recognized, an 8-bit input word The first four bits of the input word assign the MUX is shifted into the DIN input which configures the LTC1090 configuration for the requested conversion. For a given for the next conversion. Simultaneously, the result of the channel selection, the converter will measure the voltage previous conversion is output on the DOUT line. At the end between the two channels indicated by the + and – signs of the data exchange the requested conversion begins and in the selected row of Table 1. Note that in differential CS should be brought high. After tCONV, the conversion is mode (SGL/DIFF = O) measurements are limited to four complete and the results will be available on the next data adjacent input pairs with either polarity. In single ended transfer cycle. As shown below, the result of a conversion mode, all input channels are measured with respect to is delayed by one CS cycle from the input word requesting COM. Figure 1 shows some examples of multiplexer it. assignments.
Table 1. Multiplexer Channel Selection
DIN DIN Word 1 DIN Word 2 DIN Word 3
MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION
DOUT DOUT Word 0 DOUT Word 1 DOUT Word 2
SGL/ ODD SELECT
t t Data CONV CONV A/D Data A/D
DIFF SIGN 1 0 0 1 2 3 4 5 6 7
Transfer Conversion Transfer Conversion LTC1090 • AI02 0 0 0 0 + –
2. Input Data Word
0 0 0 1 + – 0 0 1 0 + – The LTC1090 8-bit input data word is clocked into the DIN 0 0 1 1 + – input on the first eight rising SCLK edges after chip select 0 1 0 0 – + is recognized. Further inputs on the DIN pin are then ignored until the next CS cycle. The eight bits of the input 0 1 0 1 – + word are defined as follows: 0 1 1 0 – + 0 1 1 1 – + Unipolar/ Data Input (D Bipolar IN) Word: Word Length
MUX ADDRESS SINGLE ENDED CHANNEL SELECTION
SGL/ ODD/ SELECT SELECT
SGL/ ODD/ SELECT
DIFF SIGN 1 0 UNI MSBF WL1 WL0
DIFF SIGN 1 0 0 1 2 3 4 5 6 7 COM
1 0 0 0 + – MUX Address MSB First/ LSB First 1 0 0 1 + – LTC1090• AI03 1 0 1 0 + – 1 0 1 1 + – 1 1 0 0 + – 1 1 0 1 + – 1 1 1 0 + – 1 1 1 1 + – 1090fc 10
U U W U APPLICATIO S I FOR ATIO
Data transfer is initiated by a falling chip select (CS) signal.
Multiplexer (MLIX) Address
After the falling CS is recognized, an 8-bit input word The first four bits of the input word assign the MUX is shifted into the DIN input which configures the LTC1090 configuration for the requested conversion. For a given for the next conversion. Simultaneously, the result of the channel selection, the converter will measure the voltage previous conversion is output on the DOUT line. At the end between the two channels indicated by the + and – signs of the data exchange the requested conversion begins and in the selected row of Table 1. Note that in differential CS should be brought high. After tCONV, the conversion is mode (SGL/DIFF = O) measurements are limited to four complete and the results will be available on the next data adjacent input pairs with either polarity. In single ended transfer cycle. As shown below, the result of a conversion mode, all input channels are measured with respect to is delayed by one CS cycle from the input word requesting COM. Figure 1 shows some examples of multiplexer it. assignments.
Table 1. Multiplexer Channel Selection
DIN DIN Word 1 DIN Word 2 DIN Word 3
MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION
DOUT DOUT Word 0 DOUT Word 1 DOUT Word 2
SGL/ ODD SELECT
t t Data CONV CONV A/D Data A/D
DIFF SIGN 1 0 0 1 2 3 4 5 6 7
Transfer Conversion Transfer Conversion LTC1090 • AI02 0 0 0 0 + –
2. Input Data Word
0 0 0 1 + – 0 0 1 0 + – The LTC1090 8-bit input data word is clocked into the DIN 0 0 1 1 + – input on the first eight rising SCLK edges after chip select 0 1 0 0 – + is recognized. Further inputs on the DIN pin are then ignored until the next CS cycle. The eight bits of the input 0 1 0 1 – + word are defined as follows: 0 1 1 0 – + 0 1 1 1 – + Unipolar/ Data Input (D Bipolar IN) Word: Word Length
MUX ADDRESS SINGLE ENDED CHANNEL SELECTION
SGL/ ODD/ SELECT SELECT
SGL/ ODD/ SELECT
DIFF SIGN 1 0 UNI MSBF WL1 WL0
DIFF SIGN 1 0 0 1 2 3 4 5 6 7 COM
1 0 0 0 + – MUX Address MSB First/ LSB First 1 0 0 1 + – LTC1090• AI03 1 0 1 0 + – 1 0 1 1 + – 1 1 0 0 + – 1 1 0 1 + – 1 1 1 0 + – 1 1 1 1 + – 1090fc 10