LTC1096/LTC1096L LTC1098/LTC1098L RECOMMENDED OPERATING CONDITIONSLTC1096/LTC1098SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS tWHCS CS High Time Between Data Transfer Cycles VCC = 5V 1 μs tWLCS CS Low Time During Data Transfer LTC1096, fCLK = 500kHz 28 μs LTC1098, fCLK = 500kHz 28 μs VCC = 3V Operation fCLK Clock Frequency VCC = 3V 25 250 kHz tCYC Total Cycle Time LTC1096, fCLK = 250kHz 58 μs LTC1098, fCLK = 250kHz 58 μs thDI Hold Time, DIN After CLK↑ VCC = 3V 450 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) VCC = 3V, LTC1096 1 μs VCC = 3V, LTC1098 1 μs tWAKEUP Wake-Up Time CS↓ Before First CLK↓ After First CLK↑ VCC = 3V, LTC1096 10 μs (See Figure 1 LTC1096 Operating Sequence) Wake-Up Time CS↓ Before MSBF Bit CLK↓ VCC = 3V, LTC1098 10 μs (See Figure 2 LTC1098 Operating Sequence) tsuDI Setup Time, DIN Stable Before CLK↑ VCC = 3V 1 μs tWHCLK CLK High Time VCC = 3V 1.6 μs tWLCLK CLK Low Time VCC = 3V 1.6 μs tWHCS CS High Time Between Data Transfer Cycles VCC = 3V 2 μs tWLCS CS Low Time During Data Transfer LTC1096, fCLK = 250kHz 56 μs LTC1098, fCLK = 250kHz 56 μs LTC1096L/LTC1098LSYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS VCC Supply Voltage 2.65 4.0 V fCLK Clock Frequency VCC = 2.65V 25 250 kHz tCYC Total Cycle Time LTC1096L, fCLK = 250kHz 58 μs LTC1098L, fCLK = 250kHz 58 μs thDI Hold Time, DIN After CLK↑ VCC = 2.65V 450 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) VCC = 2.65V, LTC1096L 1 μs VCC = 2.65V, LTC1098L 1 μs tWAKEUP Wake-Up Time CS↓ Before First CLK↓ After First CLK↑ VCC = 2.65V, LTC1096L 10 μs (See Figure 1 LTC1096L Operating Sequence) Wake-Up Time CS↓ Before MSBF Bit CLK↓ VCC = 2.65V, LTC1098L 10 μs (See Figure 2 LTC1098L Operating Sequence) tsuDI Setup Time, DIN Stable Before CLK↑ VCC = 2.65V 1 μs tWHCLK CLK High Time VCC = 2.65V 1.6 μs tWLCLK CLK Low Time VCC = 2.65V 1.6 μs tWHCS CS High Time Between Data Transfer Cycles VCC = 2.65V 2 μs tWLCS CS Low Time During Data Transfer LTC1096L, fCLK = 250kHz 56 μs LTC1098L, fCLK = 250kHz 56 μs 10968fc 4