Datasheet LTC1099 (Analog Devices) - 3

制造商Analog Devices
描述High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold
页数 / 页16 / 3 — DIGITAL AND DC ELECTRICAL CHARACTERISTICS. The
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DIGITAL AND DC ELECTRICAL CHARACTERISTICS. The

DIGITAL AND DC ELECTRICAL CHARACTERISTICS The

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LTC1099
U DIGITAL AND DC ELECTRICAL CHARACTERISTICS The

denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. VCC = 5V, REF+ = 5V, REF– = 0V and TA = TMIN to TMAX unless otherwise noted. LTC1099AI/LTC1099I LTC1099AC/LTC1099C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
VIH High Level Input Voltage All Digital Inputs, VCC = 5.25V ● 2.0 2.0 V VIL Low Level Input Voltage All Digital Inputs, VCC = 4.75V ● 0.8 0.0001 0.8 V IIH High Level Input Current VIH = 5V; CS, RD, Mode ● 0.0001 1 1 µA VIH = 5V; WR ● 0.0005 3 0.0005 3 µA IIL Low Level Input Current VIL = 0V; All Digital Inputs ● –0.0001 –1 –0.0001 –1 µA VOH High Level Output Voltage DB0-DB7, OFL, INT; VCC = 4.75V IOUT = 360µA ● 2.4 4.0 2.4 4.0 V IOUT =10µA 4.7 4.7 V VOL Low Level Output Voltage DB0-DB7, OFL, INT, RDY; VCC = 4.75V IOUT =1.6mA ● 0.4 0.4 V IOZ Hi-Z Output Leakage DB0-DB7, RDY; VOUT = 5V ● 0.1 3 0.1 3 µA DB0-DB7, RDY; VOUT = 0V ● –0.1 –3 –0.1 –3 µA ISOURCE Output Source Current DB0-DB7, OFL, INT; VOUT = 0V ● –11 –6 –11 –7 mA ISINK Output Sink Current DB0-DB7, OFL, INT, RDY; VOUT = 5V ● 14 7 14 9 mA ICC Supply Current CS = WR = RD = VCC ● 11 20 11 15 mA
AC CHARACTERISTICS The

denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. VCC = 5V, REF+ = 5V, REF– = 0V and TA = TMIN to TMAX unless otherwise noted. LTC1099AI/LTC1099I LTC1099AC/LTC1099C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RD Mode (Figure 2) Pin 7 = GND
tCRD Conversion Time TA = 25°C 2.2 2.5 2.8 2.2 2.5 2.8 µs ● 5.0 3.75 µs tRDY Delay From CS↓ to RDY↓ CL = 100pF 70 70 ns tACC0 Delay From RD↓ to Output Data Valid CL = 100pF tCRD + 35 tCRD + 35 ns tINTH Delay From RD↑ to INT↑ CL = 100pF 70 70 ns t1H, t0H Delay From RD↑ to Hi-Z State on Outputs Test Circuit Figure 1 70 70 ns tP Delay Time Between Conversions 700 700 ns tACC2 Delay Time From RD↓ to Output Data Valid 70 70 ns
WR/RD Mode (Figures 3 and 4) Pin 7 = VCC
tCWR Conversion Time TA = 25°C 2.2 2.5 2.8 2.2 2.5 2.8 µs ● 5.0 3.75 µs tACC0 Delay Time From WR↓ to Output Data Valid CL = 100pF tCWR + 40 tCWR + 40 ns tACC2 Delay From RD↓ to Output Data Valid CL = 100pF 70 70 ns tINTH Delay From RD↑ to INT↑ CL = 100pF 70 70 ns tIHWR Delay From WR↓ to INT↑ CL = 100pF 240 240 ns t1H, t0H Delay From RD↑ to Hi-Z State on Outputs Test Circuit Figure 1 70 70 ns tP Delay Time Between Conversions 700 700 ns tWR Minimum WR Pulse Width 55 55 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 3:
Total unadjusted error includes offset, gain, linearity and hold step of a device may be impaired. errors.
Note 2:
All voltages are with respect to GND (Pin 10) unless otherwise
Note 4:
Reference input voltage range is guaranteed but is not tested. noted. 3