Datasheet LTC1272 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 3µs, 250kHz Sampling A/D Converter |
| 页数 / 页 | 22 / 8 — APPLICATIONS INFORMATION. Conversion Details. Figure 1. AIN Input. … |
| 文件格式/大小 | PDF / 297 Kb |
| 文件语言 | 英语 |
APPLICATIONS INFORMATION. Conversion Details. Figure 1. AIN Input. Sample-and-Hold and Dynamic Performance
该数据表的模型线
- LTC1272-3ACN#PBF LTC1272-3ACSW#PBF LTC1272-3ACSW#TRPBF LTC1272-3CCN#PBF LTC1272-3CCSW#PBF LTC1272-3CCSW#TRPBF LTC1272-8ACN#PBF LTC1272-8ACSW#PBF LTC1272-8ACSW#TRPBF LTC1272-8CCN#PBF LTC1272-8CCSW#PBF LTC1272-8CCSW#TRPBF
文件文字版本
LTC1272
APPLICATIONS INFORMATION Conversion Details
AIN SAMPLE Conversion start is controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approxi- 300Ω SI CSAMPLE mation register (SAR) is reset and the three-state data SAMPLE – outputs are enabled. Once a conversion cycle has begun HOLD it cannot be restarted. 2.7k + COMPARATOR During conversion, the internal 12-bit capacitive DAC CDAC output is sequenced by the SAR from the most significant DAC VDAC S bit (MSB) to the least significant bit (LSB). Referring to A Figure 1, the A R IN input connects to the sample-and-hold capacitor through a 300Ω/2.7k divider. The voltage divider allows the LTC1272 to convert 0V to 5V input signals 12-BIT LATCH while operating from a 4.5V supply. The conversion has LTC1272 • F01 two phases: the sample phase and the convert phase.
Figure 1. AIN Input
During the sample phase, the comparator offset is nulled by the feedback switch and the analog input is stored earity and differential nonlinearity. These specs are useful as a charge on the sample-and-hold capacitor, CSAMPLE. for characterizing an ADC’s DC or low frequency signal This phase lasts from the end of the previous conversion performance. until the next conversion is started. A minimum delay These specs alone are not adequate to fully specify the between conversions (t10) of 1µs allows enough time LTC1272 because of its high speed sampling ability. FFT for the analog input to be acquired. During the convert (Fast Fourrier Transform) test techniques are used to phase, the comparator feedback switch opens, putting characterize the LTC1272’s frequency response, distortion the comparator into the compare mode. The sample-and- and noise at the rated throughput. hold capacitor is switched to ground injecting the analog input charge onto the comparator summing junction. This By applying a low distortion sine wave and analyzing the input charge is successively compared to binary weighted digital output using a FFT algorithm, the LTC1272’s spectral charges supplied by the capacitive DAC. Bit decisions are content can be examined for frequencies outside the fun- made by the comparator (zero crossing detector) which damental. Figure 2 shows a typical LTC1272 FFT plot. checks the addition of each successive weighted bit from 0 the DAC output. The MSB decision is made 50ns (typi- –10 cally) after the second falling edge of CLK IN following a –20 conversion start. Similarly, the succeeding bit decisions –30 are made approximately 50ns after a CLK IN edge until –40 the conversion is finished. At the end of a conversion, –50 the DAC output balances the A –60 IN output charge. The SAR –70 contents (12-bit data word) which represent the A AMPLITUDE (dB) IN input –80 signal are loaded into a 12-bit latch. –90 –100
Sample-and-Hold and Dynamic Performance
–110 0 20 40 60 80 100 120 Traditionally A/D converters have been characterized by FREQUENCY (kHz) such specs as offset and full-scale errors, integral nonlin- LTC1272 • F02
Figure 2. LTC1272 Non-Averaged, 1024 Point FFT Plot. fS = 250kHz, fIN = 10kHz
1272fc 8 For more information www.linear.com/1272 Document Outline FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS INTERNAL REFERENCE CHARACTERISTICS DIGITAL AND DC ELECTRICAL CHARACTERISTICS DYNAMIC ACCURACY ANALOG INPUT TIMING CHARACTERISTICS PIN FUNCTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION REVISION HISTORY PACKAGE DESCRIPTION
APPLICATIONS INFORMATION Conversion Details
AIN SAMPLE Conversion start is controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approxi- 300Ω SI CSAMPLE mation register (SAR) is reset and the three-state data SAMPLE – outputs are enabled. Once a conversion cycle has begun HOLD it cannot be restarted. 2.7k + COMPARATOR During conversion, the internal 12-bit capacitive DAC CDAC output is sequenced by the SAR from the most significant DAC VDAC S bit (MSB) to the least significant bit (LSB). Referring to A Figure 1, the A R IN input connects to the sample-and-hold capacitor through a 300Ω/2.7k divider. The voltage divider allows the LTC1272 to convert 0V to 5V input signals 12-BIT LATCH while operating from a 4.5V supply. The conversion has LTC1272 • F01 two phases: the sample phase and the convert phase.
Figure 1. AIN Input
During the sample phase, the comparator offset is nulled by the feedback switch and the analog input is stored earity and differential nonlinearity. These specs are useful as a charge on the sample-and-hold capacitor, CSAMPLE. for characterizing an ADC’s DC or low frequency signal This phase lasts from the end of the previous conversion performance. until the next conversion is started. A minimum delay These specs alone are not adequate to fully specify the between conversions (t10) of 1µs allows enough time LTC1272 because of its high speed sampling ability. FFT for the analog input to be acquired. During the convert (Fast Fourrier Transform) test techniques are used to phase, the comparator feedback switch opens, putting characterize the LTC1272’s frequency response, distortion the comparator into the compare mode. The sample-and- and noise at the rated throughput. hold capacitor is switched to ground injecting the analog input charge onto the comparator summing junction. This By applying a low distortion sine wave and analyzing the input charge is successively compared to binary weighted digital output using a FFT algorithm, the LTC1272’s spectral charges supplied by the capacitive DAC. Bit decisions are content can be examined for frequencies outside the fun- made by the comparator (zero crossing detector) which damental. Figure 2 shows a typical LTC1272 FFT plot. checks the addition of each successive weighted bit from 0 the DAC output. The MSB decision is made 50ns (typi- –10 cally) after the second falling edge of CLK IN following a –20 conversion start. Similarly, the succeeding bit decisions –30 are made approximately 50ns after a CLK IN edge until –40 the conversion is finished. At the end of a conversion, –50 the DAC output balances the A –60 IN output charge. The SAR –70 contents (12-bit data word) which represent the A AMPLITUDE (dB) IN input –80 signal are loaded into a 12-bit latch. –90 –100
Sample-and-Hold and Dynamic Performance
–110 0 20 40 60 80 100 120 Traditionally A/D converters have been characterized by FREQUENCY (kHz) such specs as offset and full-scale errors, integral nonlin- LTC1272 • F02
Figure 2. LTC1272 Non-Averaged, 1024 Point FFT Plot. fS = 250kHz, fIN = 10kHz
1272fc 8 For more information www.linear.com/1272 Document Outline FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS INTERNAL REFERENCE CHARACTERISTICS DIGITAL AND DC ELECTRICAL CHARACTERISTICS DYNAMIC ACCURACY ANALOG INPUT TIMING CHARACTERISTICS PIN FUNCTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION REVISION HISTORY PACKAGE DESCRIPTION