Datasheet LTC1273, LTC1275, LTC1276 (Analog Devices) - 10

LTC1273 LTC1275/LTC1276
O U U W U APPLICATI S I FOR ATIO CONVERSION DETAILS
capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output The LTC1273/LTC1275/LTC1276 use a successive ap- balances the A proximation algorithm and an internal sample-and-hold IN input charge. The SAR contents (a 12-bit data word) which represent the A circuit to convert an analog signal to a 12-bit parallel or IN are loaded into the 12-bit output latches. 2-byte output. The ADCs are complete with a precision reference and an internal clock. The control logic provides
DYNAMIC PERFORMANCE
easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) The LTC1273/LTC1275/LTC1276 have an exceptionally high speed sampling capability. FFT (Fast Fourier Trans- Conversion start is controlled by the CS, RD and HBEN form) test techniques are used to characterize the ADC’s inputs. At the start of conversion the successive approxi- frequency response, distortion and noise at the rated mation register (SAR) is reset and the three-state data throughput. By applying a low distortion sine wave and outputs are enabled. Once a conversion cycle has begun analyzing the digital output using an FFT algorithm, the it cannot be restarted. ADC’s spectral content can be examined for frequencies During conversion, the internal 12-bit capacitive DAC outside the fundamental. Figure 2 shows a typical LTC1275 output is sequenced by the SAR from the most significant FFT plot. bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the A
Signal-to-Noise Ratio
IN input connects to the sample-and-hold capacitor during the acquire phase, and the comparator The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the offset is nulled by the feedback switch. In this acquire ratio between the RMS amplitude of the fundamental input phase, a minimum delay of 600ns will provide enough frequency to the RMS amplitude of all other frequency time for the sample-and-hold capacitor to acquire the components at the A/D output. The output is band limited analog signal. During the convert phase, the comparator to frequencies from above DC and below half the sampling feedback switch opens, putting the comparator into the frequency. Figure 2 shows a typical spectral content with compare mode. The input switch switches CSAMPLE to a 300kHz sampling rate and a 29kHz input. The dynamic ground, injecting the analog input charge onto the sum- performance is excellent for input frequencies up to the ming junction. This input charge is successively com- Nyquist limit of 150kHz. pared with the binary-weighted charges supplied by the 0 fSAMPLE = 300kHz SAMPLE fIN = 29.37kHz –20 C SI SAMPLE SAMPLE –40 A – IN HOLD –60 + CDAC COMPARATOR AMPLITUDE (dB) –80 DAC VDAC S –100 A R –120 0 20 40 60 80 100 120 140 160 FREQUENCY (kHz) 12-BIT LTC1273/75/76 • F02 LATCH LTC1273/75/76 • F01
Figure 1. AIN Input Figure 2. LTC1275 Nonaveraged, 1024 Point FFT Plot
127356fa 10