Datasheet LTC1274, LTC1277 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 10mW, 100ksps ADCs with 1µA Shutdown |
| 页数 / 页 | 20 / 10 — W U. TI I G DIAGRA S. CS to RD Setup Timing. CS to CONVST Setup Timing. … |
| 文件格式/大小 | PDF / 241 Kb |
| 文件语言 | 英语 |
W U. TI I G DIAGRA S. CS to RD Setup Timing. CS to CONVST Setup Timing. NAP to CONVST Wake-Up Timing (LTC1277)
该数据表的模型线
文件文字版本
LTC1274/LTC1277
W U W TI I G DIAGRA S CS to RD Setup Timing CS to CONVST Setup Timing
CS CS t1 t2 RD CONVST LTC1274/77 • TD01 LTC1274/77 • TD02
NAP to CONVST Wake-Up Timing (LTC1277) SLEEP to REFRDY Wake-Up Timing
NAP SLEEP t3 t14 CONVST REFRDY LTC1274/77 • TD03 LTC1274/77 • TD04
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
The LTC1274/LTC1277 use a successive approximation charges supplied by the capacitive DAC. Bit decisions are algorithm and an internal sample-and-hold circuit to con- made by the high speed comparator. At the end of a vert an analog signal to a 12-bit parallel output. The ADCs conversion, the DAC output balances the AIN (LTC1274) or are complete with a precision reference and an internal A + – IN – AIN (LTC1277) input charge. The SAR contents (a 12- clock. The control logic provides easy interface to micro- bit data word) which represent the AIN (LTC1274) or processors and DSPs. (Please refer to the Digital Interface A + – IN – AIN (LTC1277) are loaded into the 12-bit output latches. section for the data format.) SAMPLE Conversion start is controlled by the CS and CONVST C SI SAMPLE SAMPLE inputs. At the start of conversion the successive approxi- A – IN mation register (SAR) is reset. Once a conversion cycle COMPAR- HOLD ATOR has begun it cannot be restarted. CDAC + DAC During conversion, the internal 12-bit capacitive DAC out- VDAC S A put is sequenced by the SAR from the most significant bit R (MSB) to the least significant bit (LSB). Referring to Figure 1, the A + IN (LTC1274) or AIN (LTC1277) input con- 12-BIT LATCH nects to the sample-and-hold capacitor during the acquire 1274 • F01 phase, and the comparator offset is nulled by the feedback
Figure 1. LTC1274 A
switch. In this acquire phase, a minimum delay of 2µs will
IN Input
provide enough time for the sample-and-hold capacitor to
DYNAMIC PERFORMANCE
acquire the analog signal. During the convert phase, the comparator feedback switch opens, putting the comparator The LTC1274/LTC1277 have excellent high speed sam- into the compare mode. The input switch connects CSAMPLE pling capability. FFT (Fast Fourier Transform) test tech- to ground (LTC1274) or A – IN (LTC1277), injecting the niques are used to test the ADCs’ frequency response, analog input charge onto the summing junction. This input distortion and noise at the rated throughput. By applying charge is successively compared with the binary-weighted a low distortion sine wave and analyzing the digital output 10
W U W TI I G DIAGRA S CS to RD Setup Timing CS to CONVST Setup Timing
CS CS t1 t2 RD CONVST LTC1274/77 • TD01 LTC1274/77 • TD02
NAP to CONVST Wake-Up Timing (LTC1277) SLEEP to REFRDY Wake-Up Timing
NAP SLEEP t3 t14 CONVST REFRDY LTC1274/77 • TD03 LTC1274/77 • TD04
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
The LTC1274/LTC1277 use a successive approximation charges supplied by the capacitive DAC. Bit decisions are algorithm and an internal sample-and-hold circuit to con- made by the high speed comparator. At the end of a vert an analog signal to a 12-bit parallel output. The ADCs conversion, the DAC output balances the AIN (LTC1274) or are complete with a precision reference and an internal A + – IN – AIN (LTC1277) input charge. The SAR contents (a 12- clock. The control logic provides easy interface to micro- bit data word) which represent the AIN (LTC1274) or processors and DSPs. (Please refer to the Digital Interface A + – IN – AIN (LTC1277) are loaded into the 12-bit output latches. section for the data format.) SAMPLE Conversion start is controlled by the CS and CONVST C SI SAMPLE SAMPLE inputs. At the start of conversion the successive approxi- A – IN mation register (SAR) is reset. Once a conversion cycle COMPAR- HOLD ATOR has begun it cannot be restarted. CDAC + DAC During conversion, the internal 12-bit capacitive DAC out- VDAC S A put is sequenced by the SAR from the most significant bit R (MSB) to the least significant bit (LSB). Referring to Figure 1, the A + IN (LTC1274) or AIN (LTC1277) input con- 12-BIT LATCH nects to the sample-and-hold capacitor during the acquire 1274 • F01 phase, and the comparator offset is nulled by the feedback
Figure 1. LTC1274 A
switch. In this acquire phase, a minimum delay of 2µs will
IN Input
provide enough time for the sample-and-hold capacitor to
DYNAMIC PERFORMANCE
acquire the analog signal. During the convert phase, the comparator feedback switch opens, putting the comparator The LTC1274/LTC1277 have excellent high speed sam- into the compare mode. The input switch connects CSAMPLE pling capability. FFT (Fast Fourier Transform) test tech- to ground (LTC1274) or A – IN (LTC1277), injecting the niques are used to test the ADCs’ frequency response, analog input charge onto the summing junction. This input distortion and noise at the rated throughput. By applying charge is successively compared with the binary-weighted a low distortion sine wave and analyzing the digital output 10