Datasheet LTC1279 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 600ksps Sampling A/D Converter with Shutdown |
| 页数 / 页 | 16 / 8 — TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output … |
| 文件格式/大小 | PDF / 286 Kb |
| 文件语言 | 英语 |
TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output Float Delay. W U. TI I G DIAGRA S. CS to RD Setup Timing
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LTC1279
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND A) HIGH-Z TO VOH (t8) B) HIGH-Z TO VOL (t8) A) VOH TO HIGH-Z B) VOL TO HIGH-Z AND VOL TO VOH (t6) AND VOH TO VOL (t6) 1279 TC02 1279 TC01
W U W TI I G DIAGRA S CS to RD Setup Timing CS to CONVST Setup Timing SHDN to CONVST Wake-Up Timing
CS CS SHDN t1 t2 t3 RD CONVST CONVST 1279 TD01 1279 TD02 1279 TD03
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
SAMPLE The LTC1279 uses a successive approximation algorithm C SI SAMPLE and an internal sample-and-hold circuit to convert an SAMPLE A – analog signal to a 12-bit parallel output. The ADC is IN COMPAR- HOLD complete with a precision reference and an internal clock. ATOR + The control logic provides easy interface to microproces- CDAC sors and DSPs. (Please refer to the Digital Interface DAC V section for the data format.) DAC S A R Conversion start is controlled by the CS and CONVST inputs. At the start of conversion the successive approxi- 12-BIT mation register (SAR) is reset. Once a conversion cycle LATCH has begun it cannot be restarted. 1279 F01
Figure 1. AIN Input
During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant time for the sample-and-hold capacitor to acquire the bit (MSB) to the least significant bit (LSB). Referring to analog signal. During the convert phase, the comparator Figure 1, the AIN input connects to the sample-and-hold feedback switch opens, putting the comparator into the capacitor during the acquire phase, and the comparator compare mode. The input switch switches CSAMPLE to offset is nulled by the feedback switch. In this acquire ground, injecting the analog input charge onto the sum- phase, a minimum delay of 160ns will provide enough ming junction. This input charge is successively com- 8
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND A) HIGH-Z TO VOH (t8) B) HIGH-Z TO VOL (t8) A) VOH TO HIGH-Z B) VOL TO HIGH-Z AND VOL TO VOH (t6) AND VOH TO VOL (t6) 1279 TC02 1279 TC01
W U W TI I G DIAGRA S CS to RD Setup Timing CS to CONVST Setup Timing SHDN to CONVST Wake-Up Timing
CS CS SHDN t1 t2 t3 RD CONVST CONVST 1279 TD01 1279 TD02 1279 TD03
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
SAMPLE The LTC1279 uses a successive approximation algorithm C SI SAMPLE and an internal sample-and-hold circuit to convert an SAMPLE A – analog signal to a 12-bit parallel output. The ADC is IN COMPAR- HOLD complete with a precision reference and an internal clock. ATOR + The control logic provides easy interface to microproces- CDAC sors and DSPs. (Please refer to the Digital Interface DAC V section for the data format.) DAC S A R Conversion start is controlled by the CS and CONVST inputs. At the start of conversion the successive approxi- 12-BIT mation register (SAR) is reset. Once a conversion cycle LATCH has begun it cannot be restarted. 1279 F01
Figure 1. AIN Input
During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant time for the sample-and-hold capacitor to acquire the bit (MSB) to the least significant bit (LSB). Referring to analog signal. During the convert phase, the comparator Figure 1, the AIN input connects to the sample-and-hold feedback switch opens, putting the comparator into the capacitor during the acquire phase, and the comparator compare mode. The input switch switches CSAMPLE to offset is nulled by the feedback switch. In this acquire ground, injecting the analog input charge onto the sum- phase, a minimum delay of 160ns will provide enough ming junction. This input charge is successively com- 8