Datasheet LTC1291 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Single Chip 12-Bit Data Acquisition System |
| 页数 / 页 | 20 / 5 — TYPICAL PERFOR A CE CHAR C. A TERISTICS. Maximum Clock Rate vs Source. … |
| 文件格式/大小 | PDF / 342 Kb |
| 文件语言 | 英语 |
TYPICAL PERFOR A CE CHAR C. A TERISTICS. Maximum Clock Rate vs Source. Maximum Filter Resistor vs
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LTC1291
W U TYPICAL PERFOR A CE CHAR C A TERISTICS Maximum Clock Rate vs Source Maximum Filter Resistor vs DOUT Delay Time vs Temperature Resistance Cycle Time
250 1.0 10k V V CC = 5V CC = 5V CLK = 1MHz RFILTER 200 0.8 +VIN + ↓ (ns) Ω 1k CFILTER ≥1µF – +VIN + +IN ** ( 150 MSB-FIRST DATA 0.6 RSOURCE– – –IN FILTER 100 100 LSB-FIRST DATA 0.4 DELAY TIME FROM CLK 10 MAXIMUM R 50 0.2 OUTD MAXIMUM CLK FREQUENCY* (MHz) 0 0 1 –50 –25 0 25 50 75 100 125 100 1k 10k 100k 10 100 1k 10k R AMBIENT TEMPERATURE (°C) SOURCE– (Ω) CYCLE TIME (µs) 1291 G10 1291 G11 1291 G12
Sample-and-Hold Acquisition Input Channel Leakage Current Time vs Source Resistance vs Temperature
100 1000 VCC = 5V 900 GUARANTEED µs) TA = 25°C 0V TO 5V INPUT STEP 800 700 600 RSOURCE+ * MAXIMUM CLK FREQUENCY REPRESENTS THE CLK 10 VIN + 500 FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE 400 ERROR AT ANY CODE TRANSITION FROM ITS 1MHz – VALUE IS FIRST DETECTED 300 200 **MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR ON CHANNEL VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE S/H AQUISITION TIME TO 0.02% ( 100 INPUT CHANNEL LEAKAGE CURRENT (nA) OFF CHANNEL ERROR FROM ITS VALUE AT RFILTER = 0Ω IS FIRST 1 0 DETECTED 100 1k 10k –50 –30 –10 10 30 50 70 90 110 130 R AMBIENT TEMPERATURE (°C) SOURCE+ (Ω) 1291 G13 1291 G14
U U U PI FU CTIO S DOUT (Pin 6):
Digital Data Output. The A/D conversion
CS (Pin 1):
Chip Select Input. A logic low on this input result is shifted out of this output. enables the LTC1291.
CLK (Pin 7):
Shift Clock. This clock synchronizes the serial
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must data transfer. be free of noise with respect to GND.
VCC(VREF) (Pin 8):
Positive Supply and Reference Voltage.
GND (Pin 4):
Analog Ground. GND should be tied directly This pin provides power and defines the span of the A/D to an analog ground plane. converter. This supply must be kept free of noise and
D
ripple by bypassing directly to the analog ground plane.
IN (Pin 5):
Digital Data Input. The multiplexer address is shifted into this input. 1291fa 5
W U TYPICAL PERFOR A CE CHAR C A TERISTICS Maximum Clock Rate vs Source Maximum Filter Resistor vs DOUT Delay Time vs Temperature Resistance Cycle Time
250 1.0 10k V V CC = 5V CC = 5V CLK = 1MHz RFILTER 200 0.8 +VIN + ↓ (ns) Ω 1k CFILTER ≥1µF – +VIN + +IN ** ( 150 MSB-FIRST DATA 0.6 RSOURCE– – –IN FILTER 100 100 LSB-FIRST DATA 0.4 DELAY TIME FROM CLK 10 MAXIMUM R 50 0.2 OUTD MAXIMUM CLK FREQUENCY* (MHz) 0 0 1 –50 –25 0 25 50 75 100 125 100 1k 10k 100k 10 100 1k 10k R AMBIENT TEMPERATURE (°C) SOURCE– (Ω) CYCLE TIME (µs) 1291 G10 1291 G11 1291 G12
Sample-and-Hold Acquisition Input Channel Leakage Current Time vs Source Resistance vs Temperature
100 1000 VCC = 5V 900 GUARANTEED µs) TA = 25°C 0V TO 5V INPUT STEP 800 700 600 RSOURCE+ * MAXIMUM CLK FREQUENCY REPRESENTS THE CLK 10 VIN + 500 FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE 400 ERROR AT ANY CODE TRANSITION FROM ITS 1MHz – VALUE IS FIRST DETECTED 300 200 **MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR ON CHANNEL VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE S/H AQUISITION TIME TO 0.02% ( 100 INPUT CHANNEL LEAKAGE CURRENT (nA) OFF CHANNEL ERROR FROM ITS VALUE AT RFILTER = 0Ω IS FIRST 1 0 DETECTED 100 1k 10k –50 –30 –10 10 30 50 70 90 110 130 R AMBIENT TEMPERATURE (°C) SOURCE+ (Ω) 1291 G13 1291 G14
U U U PI FU CTIO S DOUT (Pin 6):
Digital Data Output. The A/D conversion
CS (Pin 1):
Chip Select Input. A logic low on this input result is shifted out of this output. enables the LTC1291.
CLK (Pin 7):
Shift Clock. This clock synchronizes the serial
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must data transfer. be free of noise with respect to GND.
VCC(VREF) (Pin 8):
Positive Supply and Reference Voltage.
GND (Pin 4):
Analog Ground. GND should be tied directly This pin provides power and defines the span of the A/D to an analog ground plane. converter. This supply must be kept free of noise and
D
ripple by bypassing directly to the analog ground plane.
IN (Pin 5):
Digital Data Input. The multiplexer address is shifted into this input. 1291fa 5