Datasheet LTC1400 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Complete SO-8, 12-Bit, 400ksps ADC with Shutdown |
| 页数 / 页 | 20 / 6 — PI FU CTIO S. VCC (Pin 1):. CLK (Pin 6):. IN (Pin 2):. CONV (Pin 7):. REF … |
| 文件格式/大小 | PDF / 588 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. VCC (Pin 1):. CLK (Pin 6):. IN (Pin 2):. CONV (Pin 7):. REF (Pin 3):. GND (Pin 4):. VSS (Pin 8):. DOUT (Pin 5):
该数据表的模型线
文件文字版本
LTC1400
U U U PI FU CTIO S VCC (Pin 1):
Positive Supply, 5V. Bypass to GND (10μF
CLK (Pin 6):
Clock. This clock synchronizes the serial data tantalum in parallel with 0.1μF ceramic). transfer. A minimum CLK pulse of 50ns will cause the ADC
A
to wake up from Nap or Sleep mode.
IN (Pin 2):
Analog Input. 0V to 4.096V (Unipolar), ±2.048V (Bipolar).
CONV (Pin 7):
Conversion Start Signal. This active high
V
signal starts a conversion on its rising edge. Keeping CLK
REF (Pin 3):
2.42V Reference Output. Bypass to GND (10 low and pulsing CONV two/four times will put the ADC μF tantalum in parallel with 0.1μF ceramic). into Nap/Sleep mode.
GND (Pin 4):
Ground. GND should be tied directly to an analog ground plane.
VSS (Pin 8):
Negative Supply. –5V for bipolar operation. Bypass to GND with 0.1μF ceramic. VSS should be tied to
DOUT (Pin 5):
The A/D conversion result is shifted out GND for unipolar operation. from this pin.
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE ZEROING SWITCH A V IN CC GND VSS VREF 2.42V REF 12-BIT CAPACITIVE DAC COMP CLK CONTROL 12 LOGIC CONV SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO DOUT SERIAL CONVERTER 1400 BD01
TEST CIRCUITS
5V 3k DOUT DOUT 3k CLOAD CLOAD Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL VOH TO Hi-Z VOL TO Hi-Z 1400 TC01 1400fa 6
U U U PI FU CTIO S VCC (Pin 1):
Positive Supply, 5V. Bypass to GND (10μF
CLK (Pin 6):
Clock. This clock synchronizes the serial data tantalum in parallel with 0.1μF ceramic). transfer. A minimum CLK pulse of 50ns will cause the ADC
A
to wake up from Nap or Sleep mode.
IN (Pin 2):
Analog Input. 0V to 4.096V (Unipolar), ±2.048V (Bipolar).
CONV (Pin 7):
Conversion Start Signal. This active high
V
signal starts a conversion on its rising edge. Keeping CLK
REF (Pin 3):
2.42V Reference Output. Bypass to GND (10 low and pulsing CONV two/four times will put the ADC μF tantalum in parallel with 0.1μF ceramic). into Nap/Sleep mode.
GND (Pin 4):
Ground. GND should be tied directly to an analog ground plane.
VSS (Pin 8):
Negative Supply. –5V for bipolar operation. Bypass to GND with 0.1μF ceramic. VSS should be tied to
DOUT (Pin 5):
The A/D conversion result is shifted out GND for unipolar operation. from this pin.
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE ZEROING SWITCH A V IN CC GND VSS VREF 2.42V REF 12-BIT CAPACITIVE DAC COMP CLK CONTROL 12 LOGIC CONV SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO DOUT SERIAL CONVERTER 1400 BD01
TEST CIRCUITS
5V 3k DOUT DOUT 3k CLOAD CLOAD Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL VOH TO Hi-Z VOL TO Hi-Z 1400 TC01 1400fa 6