Datasheet LTC1401 (Analog Devices) - 7

LTC1401
U U W U APPLICATIONS INFORMATION Conversion Details
output balances the AIN input charge. The SAR contents (a 12-bit data word) which represent the input voltage, are The LTC1401 uses a successive approximation algorithm presented through the serial pin D and an internal sample-and-hold circuit to convert an OUT. analog signal to a 12-bit serial output based on a precision
Dynamic Performance
internal reference. The control logic provides an easy interface to microprocessors and DSPs through serial The LTC1401 has excellent high speed sampling capabil- 3-wire connections. ity. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise A rising edge on the CONV input starts a conversion. At the at the rated throughput. By applying a low distortion sine start of a conversion the successive approximation regis- wave and analyzing the digital output using an FFT algo- ter (SAR) is reset. Once a conversion cycle has begun, it rithm, the ADC’s spectral content can be examined for cannot be restarted. frequencies outside the fundamental. Figure 2a shows a During conversion, the internal 12-bit capacitive DAC typical LTC1401 FFT plot. output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to 0 f –10 SAMPLE = 200kHz Figure 1, the A f IN input connects to the sample-and-hold IN = 49.853516kHz –20 SINAD = 68.5dB capacitor during the acquire phase and the comparator –30 THD = –72.4dB V offset is nulled by the feedback switch. In this acquire –40 CC = 3V TA = 25°C phase, it typically takes 315ns for the sample-and-hold –50 – 60 capacitor to acquire the analog signal. During the convert –70 phase, the comparator feedback switch opens, putting the AMPLITUDE (dB) –80 comparator into the compare mode. The input switches –90 –100 CSAMPLE to ground, injecting the analog input charge onto –110 the summing junction. This input charge is successively –120 compared with the binary-weighted charges supplied by 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) the capacitive DAC. Bit decisions are made by the high LTC1401 • F02a speed comparator. At the end of a conversion, the DAC
Figure 2a. LTC1401 Nonaveraged, 4096 Point FFT Plot with 50kHz Input Frequency
SAMPLE S1 CSAMPLE SAMPLE –
Signal-to-Noise Ratio
AIN The signal-to-noise plus distortion ratio [S/(N+D)] is the COMP HOLD DAC + ratio between the RMS amplitude of the fundamental input CDAC frequency to the RMS amplitude of all other frequency S components at the A/D output. The output is band limited VDAC A R to frequencies from DC to half the sampling frequency. Figure 2a shows a typical spectral content with a 200kHz DOUT sampling rate and a 50kHz input. The dynamic perfor- LTC1401 • F01 mance is excellent for input frequencies up to the Nyquist
Figure 1. AIN Input
limit of 100kHz as shown in Figure 2b. 1401fa 7