Datasheet LTC1407, LTC1407A (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown |
| 页数 / 页 | 24 / 8 — PIN FUNCTIONS CH0+ (Pin 1):. VDD (Pin 7):. CH0– (Pin 2):. VREF (Pin 3):. … |
| 文件格式/大小 | PDF / 408 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS CH0+ (Pin 1):. VDD (Pin 7):. CH0– (Pin 2):. VREF (Pin 3):. SDO (Pin 8):. SCK (Pin 9):. CH1+ (Pin 4):. CONV (Pin 10):
该数据表的模型线
- LTC1407ACMSE#PBF LTC1407ACMSE#TRPBF LTC1407AHMSE#PBF LTC1407AHMSE#TRPBF LTC1407AIMSE#PBF LTC1407AIMSE#TRPBF LTC1407CMSE#PBF LTC1407CMSE#PBF LTC1407CMSE#TRPBF LTC1407CMSE#TRPBF LTC1407HMSE#PBF LTC1407HMSE#PBF LTC1407HMSE#TRPBF LTC1407HMSE#TRPBF LTC1407IMSE#PBF LTC1407IMSE#PBF LTC1407IMSE#TRPBF LTC1407IMSE#TRPBF
文件文字版本
LTC1407/LTC1407A
PIN FUNCTIONS CH0+ (Pin 1):
Noninverting Channel 0. CH0+ operates
VDD (Pin 7):
3V Positive Supply. This single power pin fully differentially with respect to CH0– with a 0V to 2.5V supplies 3V to the entire chip. Bypass to GND pin and differential swing and a 0 to VDD absolute input range. solid analog ground plane with a 10μF ceramic capacitor (or 10μF tantalum) in parallel with 0.1μF ceramic. Keep in
CH0– (Pin 2):
Inverting Channel 0. CH0– operates fully mind that internal analog currents and digital output signal differentially with respect to CH0+ with a –2.5V to 0V dif- currents fl ow through this pin. Care should be taken to ferential swing and a 0 to VDD absolute input range. place the 0.1μF bypass capacitor as close to Pins 6 and 7
VREF (Pin 3):
2.5V Internal Reference. Bypass to GND and as possible. a solid analog ground plane with a 10μF ceramic capacitor
SDO (Pin 8):
Three-State Serial Data Output. Each pair of (or 10μF tantalum in parallel with 0.1μF ceramic). Can be output data words represent the two analog input channels overdriven by an external reference voltage ≥ 2.55V and at the start of the previous conversion. ≤VDD.
SCK (Pin 9):
External Clock Input. Advances the conver-
CH1+ (Pin 4):
Noninverting Channel 1. CH1+ operates sion process and sequences the output data on the rising fully differentially with respect to CH1– with a 0V to 2.5V edge. One or more pulses wake from sleep. differential swing and a 0 to VDD absolute input range.
CONV (Pin 10):
Convert Start. Holds the two analog input
CH1– (Pin 5):
Inverting Channel 1. CH1– operates fully signals and starts the conversion on the rising edge. Two differentially with respect to CH1+ with a –2.5V to 0V dif- pulses with SCK in fi xed high or fi xed low state starts Nap ferential swing and a 0 to VDD absolute input range. mode. Four or more pulses with SCK in fi xed high or fi xed
GND (Pins 6, 11):
Ground and Exposed Pad. This single low state starts Sleep mode. ground pin and the Exposed Pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents fl ow through these connections.
BLOCK DIAGRAM
10μF 3V 7 VDD LTC1407A CH0+ 1 + TCH S AND H CH0– 2 – THREE- 14-BIT LA STATE 3Msps MUX SERIAL 8 SDO 14-BIT ADC OUTPUT CH1+ TCH 4 + PORT S AND H CH1– 14-BIT LA 5 – 10 CONV TIMING VREF LOGIC 3 9 SCK 10μF GND 2.5V 6 REFERENCE 11 EXPOSED PAD 1407A BD 1407fb 8
PIN FUNCTIONS CH0+ (Pin 1):
Noninverting Channel 0. CH0+ operates
VDD (Pin 7):
3V Positive Supply. This single power pin fully differentially with respect to CH0– with a 0V to 2.5V supplies 3V to the entire chip. Bypass to GND pin and differential swing and a 0 to VDD absolute input range. solid analog ground plane with a 10μF ceramic capacitor (or 10μF tantalum) in parallel with 0.1μF ceramic. Keep in
CH0– (Pin 2):
Inverting Channel 0. CH0– operates fully mind that internal analog currents and digital output signal differentially with respect to CH0+ with a –2.5V to 0V dif- currents fl ow through this pin. Care should be taken to ferential swing and a 0 to VDD absolute input range. place the 0.1μF bypass capacitor as close to Pins 6 and 7
VREF (Pin 3):
2.5V Internal Reference. Bypass to GND and as possible. a solid analog ground plane with a 10μF ceramic capacitor
SDO (Pin 8):
Three-State Serial Data Output. Each pair of (or 10μF tantalum in parallel with 0.1μF ceramic). Can be output data words represent the two analog input channels overdriven by an external reference voltage ≥ 2.55V and at the start of the previous conversion. ≤VDD.
SCK (Pin 9):
External Clock Input. Advances the conver-
CH1+ (Pin 4):
Noninverting Channel 1. CH1+ operates sion process and sequences the output data on the rising fully differentially with respect to CH1– with a 0V to 2.5V edge. One or more pulses wake from sleep. differential swing and a 0 to VDD absolute input range.
CONV (Pin 10):
Convert Start. Holds the two analog input
CH1– (Pin 5):
Inverting Channel 1. CH1– operates fully signals and starts the conversion on the rising edge. Two differentially with respect to CH1+ with a –2.5V to 0V dif- pulses with SCK in fi xed high or fi xed low state starts Nap ferential swing and a 0 to VDD absolute input range. mode. Four or more pulses with SCK in fi xed high or fi xed
GND (Pins 6, 11):
Ground and Exposed Pad. This single low state starts Sleep mode. ground pin and the Exposed Pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents fl ow through these connections.
BLOCK DIAGRAM
10μF 3V 7 VDD LTC1407A CH0+ 1 + TCH S AND H CH0– 2 – THREE- 14-BIT LA STATE 3Msps MUX SERIAL 8 SDO 14-BIT ADC OUTPUT CH1+ TCH 4 + PORT S AND H CH1– 14-BIT LA 5 – 10 CONV TIMING VREF LOGIC 3 9 SCK 10μF GND 2.5V 6 REFERENCE 11 EXPOSED PAD 1407A BD 1407fb 8