Datasheet LTC1408-12 (Analog Devices) - 8

LTC1408-12
U U U PI FU CTIO S V BIP (Pin 29):
Bipolar/Unipolar Mode. The input differen-
DD (Pin 25):
3V Positive Digital Supply. This pin supplies 3V to the logic section. Bypass to DGND pin and solid tial range is 0V – 2.5V when BIP is LOW, and it is ±1.25V analog ground plane with a 10µF ceramic capacitor (or when BIP is HIGH. Must be kept in fixed state during 10µF tantalum in parallel with 0.1µF ceramic). Keep in conversion and during subsequent conversion to read mind that internal digital output signal currents flow data. When changing BIP between conversions the full through this pin. Care should be taken to place the 0.1µF acquisition time must be allowed before starting the next bypass capacitor as close to Pin 25 as possible. Pin 25 conversion. The output data is in 2’s complement must be tied to Pin 24. format for bipolar mode and straight binary format for unipolar mode.
SEL2 (Pin 26):
Most significant bit controlling the number of channels being converted. In combination with
CONV (Pin 30):
Convert Start. Holds the six analog input SEL1 and SEL0, 000 selects just the first channel (CH0) for signals and starts the conversion on CONV’s rising edge. conversion. Incrementing SELx selects additional Two CONV pulses with SCK in fixed high or fixed low state channels(CH0–CH5) for conversion. 101, 110 or 111 starts Nap mode. Four or more CONV pulses with SCK in select all 6 channels for conversion. Must be kept in a fixed fixed high or fixed low state starts Sleep mode. state during conversion and during the subsequent con-
DGND (Pin 31):
Digital Ground. This ground pin must be version to read data. tied directly to the solid ground plane. Digital input signal
SEL1 (Pin 27):
Middle significance bit controlling the currents flow through this pin. number of channels being converted. In combination with
SCK (Pin 32):
External Clock Input. Advances the conver- SEL0 and SEL2, 000 selects just the first channel (CH0) for sion process and sequences the output data at SD0 (Pin1) conversion. Incrementing SELx selects additional on the rising edge. One or more SCK pulses wake from channels for conversion. 101, 110 or 111 select all 6 sleep or nap power saving modes. 16 clock cycles are channels (CH0–CH5) for conversion. Must be kept in a needed for each of the channels that are activated by SELx fixed state during conversion and during the subsequent (Pins 26, 27, 28), up to a total of 96 clock cycles needed conversion to read data. to convert and read out all 6 channels.
SEL0 (Pin 28):
Least significant bit controlling the
EXPOSED PAD (Pin 33):
GND. Must be tied directly to the number of channels being converted. In combination with solid ground plane. SEL1 and SEL2, 000 selects just the first channel (CH0) for conversion. Incrementing SELx selects additional channels for conversion. 101, 110 or 111 select all 6 channels (CH0–CH5) for conversion. Must be kept in a fixed state during conversion and during the subsequent conversion to read data. 140812f 8