Datasheet LTC1415 (Analog Devices) - 8

LTC1415
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
with the binary weighted charges supplied by the differen- tial capacitive DAC. Bit decisions are made by the high The LTC1415 uses a successive approximation algorithm speed comparator. At the end of a conversion, the differ- and an internal sample-and-hold circuit to convert an ential DAC output balances the + A analog signal to a 12-bit parallel output. The ADC is IN and – AIN input charges. The SAR contents (a 12-bit data word) which complete with a precision reference and an internal clock. represents the difference of + A The control logic provides easy interface to microproces- IN and – AIN are loaded into the 12-bit output latches. sors and DSPs (please refer to Digital Interface section for the data format).
DYNAMIC PERFORMANCE
Conversion start is controlled by the CS and CONVST The LTC1415 has excellent high speed sampling capabil- inputs. At the start of the conversion the successive ity. FFT (Fast Fourier Transform) test techniques are used approximation register (SAR) is reset. Once a conversion to test the ADC’s frequency response, distortion and noise cycle has begun it cannot be restarted. at the rated throughput. By applying a low distortion sine During the conversion, the internal differential 12-bit wave and analyzing the digital output using a FFT algo- capacitive DAC output is sequenced by the SAR from the rithm, the ADC’s spectral content can be examined for most significant bit (MSB) to the least significant bit (LSB). frequencies outside the fundamental. Figure 2 shows a Referring to Figure 1, the +AIN and –AIN inputs are con- typical LTC1415 FFT plot. nected to the sample-and-hold capacitors (CSAMPLE) dur- ing the acquire phase and the comparator offset is nulled by 0 the zeroing switches. In this acquire phase, a minimum fSAMPLE = 1.25MHz fIN = 99.792kHz delay of 150ns will provide enough time for the sample- –20 SFDR - 87.5 SINAD = 72.1 and-hold capacitors to acquire the analog signal. During –40 the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input –60 switches the connect CSAMPLE capacitors to ground, trans- AMPLITUDE (dB) –80 ferring the differential analog input charge onto the sum- ming junction. This input charge is successively compared –100 –120 +C 0 100 200 300 400 500 600 SAMPLE SAMPLE FREQUENCY (kHz) +AIN HOLD LTC1415 • F02 ZEROING SWITCHES –CSAMPLE HOLD
Figure 2. LTC1415 Nonaveraged, 4096 Point FFT
SAMPLE –AIN HOLD HOLD
Signal-to-Noise Ratio
+CDAC The signal-to-noise plus distortion ratio [S/(N + D)] or + SINAD is the ratio between the RMS amplitude of the –C COMP DAC +VDAC – fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below –VDAC 12 • D11 SAR OUTPUT half the sampling frequency. Figure 2 shows a typical • LATCHES • D0 spectral content with a 1.25MHz sampling rate and a LTC1415 • F01 100kHz input. The dynamic performance is excellent for
Figure 1. Simplified Block Diagram
input frequencies up to the Nyquist limit of 625kHz. 8