Datasheet LTC1418 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O |
| 页数 / 页 | 30 / 8 — PIN FUNCTIONS A +. IN (Pin 1):. D0 (EXT/INT) (Pin 20):. A –. IN (Pin 2):. … |
| 文件格式/大小 | PDF / 486 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS A +. IN (Pin 1):. D0 (EXT/INT) (Pin 20):. A –. IN (Pin 2):. VREF (Pin 3):. REFCOMP (Pin 4):. SER/PAR (Pin 21):
该数据表的模型线
文件文字版本
LTC1418
PIN FUNCTIONS A + IN (Pin 1):
Positive Analog Input.
D0 (EXT/INT) (Pin 20):
Three-State Data Output (Parallel).
A –
Conversion clock selector (serial). An input low enables
IN (Pin 2):
Negative Analog Input. the internal conversion clock. An input high indicates
VREF (Pin 3):
2.50V Reference Output. Bypass to AGND an external conversion clock will be assigned to Pin 16 with 1µF. (EXTCLKIN).
REFCOMP (Pin 4):
4.096V Reference Bypass Pin. Bypass
SER/PAR (Pin 21):
Data Output Mode. to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
SHDN (Pin 22):
Power Shutdown Input. Low selects
AGND (Pin 5):
Analog Ground. shutdown. Shutdown mode selected by CS. CS = 0 for
D13 to D6 (Pins 6 to 13):
Three-State Data Outputs (Paral- nap mode and CS = 1 for sleep mode. lel). D13 is the most significant bit.
RD (Pin 23):
Read Input. This enables the output drivers
DGND (Pin 14):
Digital Ground for Internal Logic. Tie to when CS is low. AGND.
CONVST (Pin 24):
Conversion Start Signal. This active low
D5 (Pin 15):
Three-State Data Output (Parallel). signal starts a conversion on its falling edge.
D4 (EXTCLKIN) (Pin 16):
Three-State Data Output (Par-
CS (Pin 25):
Chip Select. This input must be low for the allel). Conversion clock input (serial) when Pin 20 (EXT/ ADC to recognize the CONVST and RD inputs. CS also INT) is tied high. sets the shutdown mode when SHDN goes low. CS and SHDN low select the quick wake-up nap mode. CS high
D3 (SCLK) (Pin 17):
Three-State Data Output (Parallel). and SHDN low select sleep mode. Data clock input (serial).
BUSY (Pin 26):
The BUSY Output Shows the Converter
D2 (CLKOUT) (Pin 18):
Three-State Data Output (Parallel). Status. It is low when a conversion is in progress. Conversion clock output (serial).
V D1 (D SS (Pin 27):
Negative Supply, –5V for Bipolar Operation.
OUT) (Pin 19):
Three-State Data Output (Parallel). Bypass to AGND with 10µF tantalum in parallel with 0.1µF Serial data output (serial). ceramic. Analog ground for unipolar operation.
VDD (Pin 28):
5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
TEST CIRCUITS Load Circuits for Output Float Delay Load Circuits for Access Timing
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 30pF 30pF DGND DGND A) HI-Z TO VOH AND VOL TO VOH B) HI-Z TO VOL AND VOH TO VOL A) VOH TO HI-Z B) VOL TO HI-Z 1418 TC02 1418 TC01 1418fa 8 For more information www.linear.com/LTC1418 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Package/Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Test Circuit Block Diagram Applications Information Package Description Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS A + IN (Pin 1):
Positive Analog Input.
D0 (EXT/INT) (Pin 20):
Three-State Data Output (Parallel).
A –
Conversion clock selector (serial). An input low enables
IN (Pin 2):
Negative Analog Input. the internal conversion clock. An input high indicates
VREF (Pin 3):
2.50V Reference Output. Bypass to AGND an external conversion clock will be assigned to Pin 16 with 1µF. (EXTCLKIN).
REFCOMP (Pin 4):
4.096V Reference Bypass Pin. Bypass
SER/PAR (Pin 21):
Data Output Mode. to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
SHDN (Pin 22):
Power Shutdown Input. Low selects
AGND (Pin 5):
Analog Ground. shutdown. Shutdown mode selected by CS. CS = 0 for
D13 to D6 (Pins 6 to 13):
Three-State Data Outputs (Paral- nap mode and CS = 1 for sleep mode. lel). D13 is the most significant bit.
RD (Pin 23):
Read Input. This enables the output drivers
DGND (Pin 14):
Digital Ground for Internal Logic. Tie to when CS is low. AGND.
CONVST (Pin 24):
Conversion Start Signal. This active low
D5 (Pin 15):
Three-State Data Output (Parallel). signal starts a conversion on its falling edge.
D4 (EXTCLKIN) (Pin 16):
Three-State Data Output (Par-
CS (Pin 25):
Chip Select. This input must be low for the allel). Conversion clock input (serial) when Pin 20 (EXT/ ADC to recognize the CONVST and RD inputs. CS also INT) is tied high. sets the shutdown mode when SHDN goes low. CS and SHDN low select the quick wake-up nap mode. CS high
D3 (SCLK) (Pin 17):
Three-State Data Output (Parallel). and SHDN low select sleep mode. Data clock input (serial).
BUSY (Pin 26):
The BUSY Output Shows the Converter
D2 (CLKOUT) (Pin 18):
Three-State Data Output (Parallel). Status. It is low when a conversion is in progress. Conversion clock output (serial).
V D1 (D SS (Pin 27):
Negative Supply, –5V for Bipolar Operation.
OUT) (Pin 19):
Three-State Data Output (Parallel). Bypass to AGND with 10µF tantalum in parallel with 0.1µF Serial data output (serial). ceramic. Analog ground for unipolar operation.
VDD (Pin 28):
5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
TEST CIRCUITS Load Circuits for Output Float Delay Load Circuits for Access Timing
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 30pF 30pF DGND DGND A) HI-Z TO VOH AND VOL TO VOH B) HI-Z TO VOL AND VOH TO VOL A) VOH TO HI-Z B) VOL TO HI-Z 1418 TC02 1418 TC01 1418fa 8 For more information www.linear.com/LTC1418 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Package/Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Test Circuit Block Diagram Applications Information Package Description Package Description Revision History Typical Application Related Parts