Datasheet LTC1419 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 800ksps Sampling A/D Converter with Shutdown |
| 页数 / 页 | 20 / 7 — TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output … |
| 文件格式/大小 | PDF / 270 Kb |
| 文件语言 | 英语 |
TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output Float Delay. APPLICATIONS INFORMATION
该数据表的模型线
- LTC1419ACG#PBF LTC1419ACG#PBF LTC1419ACG#TRPBF LTC1419ACG#TRPBF LTC1419ACSW#PBF LTC1419ACSW#PBF LTC1419ACSW#TRPBF LTC1419ACSW#TRPBF LTC1419AIG#PBF LTC1419AIG#PBF LTC1419AIG#TRPBF LTC1419AIG#TRPBF LTC1419AISW#PBF LTC1419AISW#PBF LTC1419AISW#TRPBF LTC1419AISW#TRPBF LTC1419CG#PBF LTC1419CG#PBF LTC1419CG#TRPBF LTC1419CG#TRPBF LTC1419CSW#PBF LTC1419CSW#PBF LTC1419CSW#TRPBF LTC1419CSW#TRPBF LTC1419IG#PBF LTC1419IG#PBF LTC1419IG#TRPBF LTC1419IG#TRPBF LTC1419ISW#PBF LTC1419ISW#PBF LTC1419ISW#TRPBF LTC1419ISW#TRPBF
文件文字版本
LTC1419
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 100pF 100pF (A) Hi-Z TO VOH (B) Hi-Z TO VO (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1419 TC01 1419 TC02
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the The LTC1419 uses a successive approximation algorithm most significant bit (MSB) to the least significant bit (LSB). and an internal sample-and-hold circuit to convert an Referring to Figure 1, the + A analog signal to a 14-bit parallel output. The ADC is IN and – AIN inputs are con- nected to the sample-and-hold capacitors (C complete with a precision reference and an internal clock. SAMPLE) dur- ing the acquire phase and the comparator offset is nulled by The control logic provides easy interface to microproces- the zeroing switches. In this acquire phase, a minimum sors and DSPs (please refer to Digital Interface section for delay of 200ns will provide enough time for the sample- the data format). and-hold capacitors to acquire the analog signal. During Conversion start is controlled by the CS and CONVST the convert phase, the comparator zeroing switches open, inputs. At the start of the conversion, the successive putting the comparator into compare mode. The input approximation register (SAR) is reset. Once a conversion switches the CSAMPLE capacitors to ground, transferring cycle has begun, it cannot be restarted. the differential analog input charge onto the summing junction. This input charge is successively compared with +CSAMPLE the binary weighted charges supplied by the differential SAMPLE +AIN capacitive DAC. Bit decisions are made by the high speed HOLD ZEROING SWITCHES comparator. At the end of a conversion, the differential –CSAMPLE HOLD SAMPLE DAC output balances the + A –A IN and – AIN input charges. IN HOLD The SAR contents (a 14-bit data word) which represents HOLD the difference of + AIN and – AIN are loaded into the 14-bit +CDAC output latches. + –C COMP DAC +VDAC
DYNAMIC PERFORMANCE
– The LTC1419 has excellent high speed sampling capabil- ity. FFT (Fast Fourier Transform) test techniques are used –VDAC 14 • D13 SAR OUTPUT to test the ADC’s frequency response, distortion and noise • LATCHES • D0 at the rated throughput. By applying a low distortion sine 1419 F01 wave and analyzing the digital output using an FFT algo-
Figure 1. Simplified Block Diagram
rithm, the ADC’s spectral content can be examined for 1419fb 7
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 100pF 100pF (A) Hi-Z TO VOH (B) Hi-Z TO VO (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1419 TC01 1419 TC02
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the The LTC1419 uses a successive approximation algorithm most significant bit (MSB) to the least significant bit (LSB). and an internal sample-and-hold circuit to convert an Referring to Figure 1, the + A analog signal to a 14-bit parallel output. The ADC is IN and – AIN inputs are con- nected to the sample-and-hold capacitors (C complete with a precision reference and an internal clock. SAMPLE) dur- ing the acquire phase and the comparator offset is nulled by The control logic provides easy interface to microproces- the zeroing switches. In this acquire phase, a minimum sors and DSPs (please refer to Digital Interface section for delay of 200ns will provide enough time for the sample- the data format). and-hold capacitors to acquire the analog signal. During Conversion start is controlled by the CS and CONVST the convert phase, the comparator zeroing switches open, inputs. At the start of the conversion, the successive putting the comparator into compare mode. The input approximation register (SAR) is reset. Once a conversion switches the CSAMPLE capacitors to ground, transferring cycle has begun, it cannot be restarted. the differential analog input charge onto the summing junction. This input charge is successively compared with +CSAMPLE the binary weighted charges supplied by the differential SAMPLE +AIN capacitive DAC. Bit decisions are made by the high speed HOLD ZEROING SWITCHES comparator. At the end of a conversion, the differential –CSAMPLE HOLD SAMPLE DAC output balances the + A –A IN and – AIN input charges. IN HOLD The SAR contents (a 14-bit data word) which represents HOLD the difference of + AIN and – AIN are loaded into the 14-bit +CDAC output latches. + –C COMP DAC +VDAC
DYNAMIC PERFORMANCE
– The LTC1419 has excellent high speed sampling capabil- ity. FFT (Fast Fourier Transform) test techniques are used –VDAC 14 • D13 SAR OUTPUT to test the ADC’s frequency response, distortion and noise • LATCHES • D0 at the rated throughput. By applying a low distortion sine 1419 F01 wave and analyzing the digital output using an FFT algo-
Figure 1. Simplified Block Diagram
rithm, the ADC’s spectral content can be examined for 1419fb 7