Datasheet LTC1606 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 250ksps, Single Supply ADC |
| 页数 / 页 | 16 / 7 — PI FU CTIO S. VIN (Pin 1):. AGND1 (Pin 2):. R/C (Pin 24):. REF (Pin 3):. … |
| 文件格式/大小 | PDF / 205 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. VIN (Pin 1):. AGND1 (Pin 2):. R/C (Pin 24):. REF (Pin 3):. CS (Pin 25):. CAP (Pin 4):. AGND2 (Pin 5):. BUSY (Pin 26):
该数据表的模型线
- LTC1606ACG#PBF LTC1606ACG#PBF LTC1606ACG#TRPBF LTC1606ACG#TRPBF LTC1606ACSW#PBF LTC1606ACSW#PBF LTC1606ACSW#TRPBF LTC1606ACSW#TRPBF LTC1606AIG#PBF LTC1606AIG#PBF LTC1606AIG#TRPBF LTC1606AIG#TRPBF LTC1606AISW#PBF LTC1606AISW#PBF LTC1606AISW#TRPBF LTC1606AISW#TRPBF LTC1606CG#PBF LTC1606CG#PBF LTC1606CG#TRPBF LTC1606CG#TRPBF LTC1606CSW#PBF LTC1606CSW#PBF LTC1606CSW#TRPBF LTC1606CSW#TRPBF LTC1606IG#PBF LTC1606IG#PBF LTC1606IG#TRMPBF LTC1606IG#TRPBF LTC1606IG#TRPBF LTC1606ISW#PBF LTC1606ISW#PBF LTC1606ISW#TRPBF LTC1606ISW#TRPBF
文件文字版本
LTC1606
U U U PI FU CTIO S VIN (Pin 1):
Analog Input. Connect through a 200Ω being the LSB. With BYTE high, the upper eight bits and resistor to the analog input. Full-scale input range is the lower eight bits will be switched. The MSB is output ±10V. on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on Pin 6 and the LSB is output on Pin 13.
AGND1 (Pin 2):
Analog Ground. Tie to analog ground plane.
R/C (Pin 24):
Read/Convert Input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the
REF (Pin 3):
2.5V Reference Output. Bypass with 2.2µF hold state and starts a conversion. With CS low, a rising tantalum capacitor. Can be driven with an external edge on R/C enables the output data bits. reference.
CS (Pin 25):
Chip Select. Internally OR’d with R/C. With
CAP (Pin 4):
Reference Buffer Output. Bypass with 10µF R/C low, a falling edge on CS will initiate a conversion. tantalum capacitor. The capacitor output voltage is 4.096V With R/C high, a falling edge on CS will enable the output when REF = 2.5V. data.
AGND2 (Pin 5):
Analog Ground. Tie to analog ground
BUSY (Pin 26):
Output Shows Converter Status. It is low plane. when a conversion is in progress. Data valid on the rising
D15 to D8 (Pins 6 to 13):
Three-State Data Outputs. edge of BUSY. CS or R/C must be high when BUSY rises Hi-Z state when CS is high or when R/C is low. or another conversion will start without time for signal
DGND (Pin 14):
Digital Ground. acquisition.
D7 to D0 (Pins 15 to 22):
Three-State Data Outputs.
VANA (Pin 27):
5V Analog Supply. Bypass to ground with Hi-Z state when CS is high or when R/C is low. a 0.1µF ceramic and a 10µF tantalum capacitor.
BYTE (Pin 23):
Byte Select. With BYTE low, data will be
VDIG (Pin 28):
5V Digital Supply. Connect directly to output with Pin 6 (D15) being the MSB and Pin 22 (D0) Pin 27.
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE 7.35k VIN V 9k 2.5k ANA CSAMPLE VDIG ZEROING SWITCHES 4k REF 2.5V REF + REF BUF 16-BIT CAPACITIVE DAC COMP 1.64x – CAP (4.096V) 16 SUCCESSIVE APPROXIMATION • D15 OUTPUT LATCHES • REGISTER • D0 AGND1 AGND2 INTERNAL CONTROL LOGIC DGND CLOCK 1606 BD CS R/C BYTE BUSY 1606fa 7
U U U PI FU CTIO S VIN (Pin 1):
Analog Input. Connect through a 200Ω being the LSB. With BYTE high, the upper eight bits and resistor to the analog input. Full-scale input range is the lower eight bits will be switched. The MSB is output ±10V. on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on Pin 6 and the LSB is output on Pin 13.
AGND1 (Pin 2):
Analog Ground. Tie to analog ground plane.
R/C (Pin 24):
Read/Convert Input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the
REF (Pin 3):
2.5V Reference Output. Bypass with 2.2µF hold state and starts a conversion. With CS low, a rising tantalum capacitor. Can be driven with an external edge on R/C enables the output data bits. reference.
CS (Pin 25):
Chip Select. Internally OR’d with R/C. With
CAP (Pin 4):
Reference Buffer Output. Bypass with 10µF R/C low, a falling edge on CS will initiate a conversion. tantalum capacitor. The capacitor output voltage is 4.096V With R/C high, a falling edge on CS will enable the output when REF = 2.5V. data.
AGND2 (Pin 5):
Analog Ground. Tie to analog ground
BUSY (Pin 26):
Output Shows Converter Status. It is low plane. when a conversion is in progress. Data valid on the rising
D15 to D8 (Pins 6 to 13):
Three-State Data Outputs. edge of BUSY. CS or R/C must be high when BUSY rises Hi-Z state when CS is high or when R/C is low. or another conversion will start without time for signal
DGND (Pin 14):
Digital Ground. acquisition.
D7 to D0 (Pins 15 to 22):
Three-State Data Outputs.
VANA (Pin 27):
5V Analog Supply. Bypass to ground with Hi-Z state when CS is high or when R/C is low. a 0.1µF ceramic and a 10µF tantalum capacitor.
BYTE (Pin 23):
Byte Select. With BYTE low, data will be
VDIG (Pin 28):
5V Digital Supply. Connect directly to output with Pin 6 (D15) being the MSB and Pin 22 (D0) Pin 27.
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE 7.35k VIN V 9k 2.5k ANA CSAMPLE VDIG ZEROING SWITCHES 4k REF 2.5V REF + REF BUF 16-BIT CAPACITIVE DAC COMP 1.64x – CAP (4.096V) 16 SUCCESSIVE APPROXIMATION • D15 OUTPUT LATCHES • REGISTER • D0 AGND1 AGND2 INTERNAL CONTROL LOGIC DGND CLOCK 1606 BD CS R/C BYTE BUSY 1606fa 7