Datasheet LTC1608 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | High Speed, 16-Bit, 500ksps Sampling A/D Converter with Shutdown |
| 页数 / 页 | 20 / 8 — APPLICATIO S I FOR ATIO. 3V Input/Output Compatible. Power Shutdown. … |
| 文件格式/大小 | PDF / 816 Kb |
| 文件语言 | 英语 |
APPLICATIO S I FOR ATIO. 3V Input/Output Compatible. Power Shutdown. Figure 1. Simplified Block Diagram. DIGITAL INTERFACE
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LTC1608
U U W U APPLICATIO S I FOR ATIO 3V Input/Output Compatible
CSMPL SAMPLE A + IN The LTC1608 operates on ±5V supplies, which makes the HOLD device easy to interface to 5V digital systems. This device ZEROING SWITCHES can also talk to 3V digital systems: the digital input pins CSMPL HOLD SAMPLE (SHDN, CS, CONVST and RD) of the LTC1608 recognize A – IN HOLD 3V or 5V inputs. The LTC1608 has a dedicated output HOLD supply pin (OVDD) that controls the output swings of the +CDAC digital output pins (D0 to D15, BUSY) and allows the part + to talk to either 3V or 5V digital systems. The output is –CDAC COMP two’s complement binary. – +VDAC
Power Shutdown
–VDAC The LTC1608 provides two power shutdown modes, Nap 16 D15 OUTPUT • SAR • and Sleep, to save power during inactive periods. The Nap LATCHES • D0 mode reduces the power by 95% and leaves only the 1608 F01 digital logic and reference powered up. The wake-up time
Figure 1. Simplified Block Diagram
from Nap to active is 200ns. In Sleep mode, all bias currents are shut down and only leakage current remains (about 1µA). Wake-up time from Sleep mode is much compared with the binary-weighted charges supplied by longer since the reference circuit must power up and the differential capacitive DAC. Bit decisions are made by settle. Sleep mode wake-up time is dependent on the the high speed comparator. At the end of a conversion, the value of the capacitor connected to the REFCOMP (Pin 4). differential DAC output balances the A + – IN and AIN input The wake-up time is 80ms with the recommended 22µF charges. The SAR contents (a 16-bit data word) which capacitor. represent the difference of A + – IN and AIN are loaded into the 16-bit output latches. Shutdown is controlled by Pin 33 (SHDN). The ADC is in shutdown when SHDN is low. The shutdown mode is
DIGITAL INTERFACE
selected with Pin 32 (CS). When SHDN is low, CS low The A/D converter is designed to interface with micropro- selects nap and CS high selects sleep. cessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory SHDN interfacing. A separate CONVST is used to initiate a con- t3 version. CS 1608 F02a
Internal Clock
The A/D converter has an internal clock that runs the A/D
Figure 2a. Nap Mode to Sleep Mode Timing
conversion. The internal clock is factory trimmed to achieve a typical conversion time of 1.45µs and a maximum SHDN conversion time of 1.8µs over the full temperature range. No external adjustments are required. The guaranteed t4 maximum acquisition time is 400ns. In addition, a through- CONVST 1608 F02b put time (acquisition + conversion) of 2µs and a minimum sampling rate of 500ksps are guaranteed.
Figure 2b. SHDN to CONVST Wake-Up Timing
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U U W U APPLICATIO S I FOR ATIO 3V Input/Output Compatible
CSMPL SAMPLE A + IN The LTC1608 operates on ±5V supplies, which makes the HOLD device easy to interface to 5V digital systems. This device ZEROING SWITCHES can also talk to 3V digital systems: the digital input pins CSMPL HOLD SAMPLE (SHDN, CS, CONVST and RD) of the LTC1608 recognize A – IN HOLD 3V or 5V inputs. The LTC1608 has a dedicated output HOLD supply pin (OVDD) that controls the output swings of the +CDAC digital output pins (D0 to D15, BUSY) and allows the part + to talk to either 3V or 5V digital systems. The output is –CDAC COMP two’s complement binary. – +VDAC
Power Shutdown
–VDAC The LTC1608 provides two power shutdown modes, Nap 16 D15 OUTPUT • SAR • and Sleep, to save power during inactive periods. The Nap LATCHES • D0 mode reduces the power by 95% and leaves only the 1608 F01 digital logic and reference powered up. The wake-up time
Figure 1. Simplified Block Diagram
from Nap to active is 200ns. In Sleep mode, all bias currents are shut down and only leakage current remains (about 1µA). Wake-up time from Sleep mode is much compared with the binary-weighted charges supplied by longer since the reference circuit must power up and the differential capacitive DAC. Bit decisions are made by settle. Sleep mode wake-up time is dependent on the the high speed comparator. At the end of a conversion, the value of the capacitor connected to the REFCOMP (Pin 4). differential DAC output balances the A + – IN and AIN input The wake-up time is 80ms with the recommended 22µF charges. The SAR contents (a 16-bit data word) which capacitor. represent the difference of A + – IN and AIN are loaded into the 16-bit output latches. Shutdown is controlled by Pin 33 (SHDN). The ADC is in shutdown when SHDN is low. The shutdown mode is
DIGITAL INTERFACE
selected with Pin 32 (CS). When SHDN is low, CS low The A/D converter is designed to interface with micropro- selects nap and CS high selects sleep. cessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory SHDN interfacing. A separate CONVST is used to initiate a con- t3 version. CS 1608 F02a
Internal Clock
The A/D converter has an internal clock that runs the A/D
Figure 2a. Nap Mode to Sleep Mode Timing
conversion. The internal clock is factory trimmed to achieve a typical conversion time of 1.45µs and a maximum SHDN conversion time of 1.8µs over the full temperature range. No external adjustments are required. The guaranteed t4 maximum acquisition time is 400ns. In addition, a through- CONVST 1608 F02b put time (acquisition + conversion) of 2µs and a minimum sampling rate of 500ksps are guaranteed.
Figure 2b. SHDN to CONVST Wake-Up Timing
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