Datasheet LTC1609 (Analog Devices) - 8

LTC1609
U U W FUNCTIONAL BLOCK DIAGRA
CSAMPLE 20k R1IN 10k V R2 20k ANA IN CSAMPLE 5k R3IN VDIG ZEROING SWITCHES 4k REF 2.5V REF + REF BUF 16-BIT CAPACITIVE DAC COMP – CAP (2.5V) DATA SUCCESSIVE APPROXIMATION REGISTER SERIAL INTERFACE DATACLK AGND1 AGND2 SYNC INTERNAL CONTROL LOGIC DGND CLOCK 1609 BD CS R/C PWRD BUSY SB/BTC EXT/INT TAG
U U W U APPLICATIO S I FOR ATIO Conversion Details
the analog signal. During the convert phase, the autozero switches open, putting the comparator into the compare The LTC1609 uses a successive approximation algorithm mode. The input switch switches C and an internal sample-and-hold circuit to convert an SAMPLE to ground, injecting the analog input charge onto the summing junc- analog signal to a 16-bit serial output. The ADC is complete tion. This input charge is successively compared with the with a precision reference and an internal clock. The binary-weighted charges supplied by the capacitive DAC. control logic provides easy interface to microprocessors Bit decisions are made by the high speed comparator. At and DSPs. (Please refer to the Digital Interface section for timing information.) SAMPLE Conversion start is controlled by the CS and R/C inputs. At C SI the start of conversion the successive approximation RIN1 SAMPLE SAMPLE VIN – register (SAR) is reset. Once a conversion cycle has begun HOLD it cannot be restarted. RIN2 + C During the conversion, the internal 16-bit capacitive DAC DAC COMPARATOR DAC output is sequenced by the SAR from the most significant VDAC S bit (MSB) to the least significant bit (LSB). Referring to A R Figure 1, VIN is connected through the resistor divider to the sample-and-hold capacitor during the acquire phase 16-BIT and the comparator offset is nulled by the autozero switches. SHIFT REGISTER 1609 F01 In this acquire phase, a minimum delay of 2µs will provide enough time for the sample-and-hold capacitor to acquire
Figure 1. LTC1609 Simplified Equivalent Circuit
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