Datasheet LTC1741 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 65Msps Low Noise ADC |
| 页数 / 页 | 20 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 65Msps. 72dB SNR and 85dB SFDR (3.2V … |
| 文件格式/大小 | PDF / 682 Kb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTIO. Sample Rate: 65Msps. 72dB SNR and 85dB SFDR (3.2V Range). 70.5dB SNR and 87dB SFDR (2V Range). APPLICATIO S
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LTC1741 12-Bit, 65Msps Low Noise ADC
U FEATURES DESCRIPTIO
■
Sample Rate: 65Msps
The LTC®1741 is an 65Msps, sampling 12-bit A/D con- ■
72dB SNR and 85dB SFDR (3.2V Range)
verter designed for digitizing high frequency, wide dy- ■
70.5dB SNR and 87dB SFDR (2V Range)
namic range signals. Pin selectable input ranges of ±1V ■ No Missing Codes and ±1.6V along with a resistor programmable mode ■ Single 5V Supply allow the LTC1741’s input range to be optimized for a wide ■ Power Dissipation: 1.275W variety of applications. ■ Selectable Input Ranges: ±1V or ±1.6V The LTC1741 is perfect for demanding communications ■ 240MHz Full Power Bandwidth S/H applications with AC performance that includes 72dB ■ Pin Compatible Family SNR and 85dB spurious free dynamic range. Ultralow jitter 25Msps: LTC1746 (14-Bit), LTC1745(12-Bit) of 0.15ps 50Msps: LTC1744 (14-Bit), LTC1743(12-Bit) RMS allows undersampling of IF frequencies of up to 70MHz with excellent noise performance. DC specs 65Msps: LTC1742 (14-Bit), LTC1741(12-Bit) include ±1 LSB INL and ±0.8LSB DNL over temperature. 80Msps: LTC1748 (14-Bit), LTC1747(12-Bit) ■ 48-Pin TSSOP Package The digital interface is compatible with 5V, 3V, 2V and
U
LVDS logic systems. The ENC and ENC inputs may be
APPLICATIO S
driven differentially from PECL, GTL and other low swing logic families or from single-ended TTL or CMOS. The low ■ Telecommunications noise, high gain ENC and ENC inputs may also be driven ■ Receivers by a sinusoidal signal without degrading performance. A ■ Cellular Base Stations separate output power supply can be operated from 0.5V ■ Spectrum Analysis to 5V, making it easy to connect directly to any low voltage ■ Imaging Systems DSPs or FIFOs. , LTC and LT are registered trademarks of Linear Technology Corporation. The TSSOP package with a flow-through pinout simplifies the board layout.
W BLOCK DIAGRA 65Msps, 12-Bit ADC with a
±
1V Differential Input Range
OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN OF ±1V CORRECTION 12 D11 DIFFERENTIAL S/H 12-BIT LOGIC AND OUTPUT • • ANALOG INPUT AMP PIPELINED ADC SHIFT LATCHES • A – D0 IN REGISTER CLKOUT OGND SENSE BUFFER VDD 5V RANGE 1µF 1µF SELECT DIFF AMP 1µF VCM GND 2.35VREF CONTROL LOGIC 4.7µF 1741 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV OE 4.7µF 0.1µF 0.1µF DIFFERENTIAL 1µF 1µF ENCODE INPUT 1741f 1
U FEATURES DESCRIPTIO
■
Sample Rate: 65Msps
The LTC®1741 is an 65Msps, sampling 12-bit A/D con- ■
72dB SNR and 85dB SFDR (3.2V Range)
verter designed for digitizing high frequency, wide dy- ■
70.5dB SNR and 87dB SFDR (2V Range)
namic range signals. Pin selectable input ranges of ±1V ■ No Missing Codes and ±1.6V along with a resistor programmable mode ■ Single 5V Supply allow the LTC1741’s input range to be optimized for a wide ■ Power Dissipation: 1.275W variety of applications. ■ Selectable Input Ranges: ±1V or ±1.6V The LTC1741 is perfect for demanding communications ■ 240MHz Full Power Bandwidth S/H applications with AC performance that includes 72dB ■ Pin Compatible Family SNR and 85dB spurious free dynamic range. Ultralow jitter 25Msps: LTC1746 (14-Bit), LTC1745(12-Bit) of 0.15ps 50Msps: LTC1744 (14-Bit), LTC1743(12-Bit) RMS allows undersampling of IF frequencies of up to 70MHz with excellent noise performance. DC specs 65Msps: LTC1742 (14-Bit), LTC1741(12-Bit) include ±1 LSB INL and ±0.8LSB DNL over temperature. 80Msps: LTC1748 (14-Bit), LTC1747(12-Bit) ■ 48-Pin TSSOP Package The digital interface is compatible with 5V, 3V, 2V and
U
LVDS logic systems. The ENC and ENC inputs may be
APPLICATIO S
driven differentially from PECL, GTL and other low swing logic families or from single-ended TTL or CMOS. The low ■ Telecommunications noise, high gain ENC and ENC inputs may also be driven ■ Receivers by a sinusoidal signal without degrading performance. A ■ Cellular Base Stations separate output power supply can be operated from 0.5V ■ Spectrum Analysis to 5V, making it easy to connect directly to any low voltage ■ Imaging Systems DSPs or FIFOs. , LTC and LT are registered trademarks of Linear Technology Corporation. The TSSOP package with a flow-through pinout simplifies the board layout.
W BLOCK DIAGRA 65Msps, 12-Bit ADC with a
±
1V Differential Input Range
OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN OF ±1V CORRECTION 12 D11 DIFFERENTIAL S/H 12-BIT LOGIC AND OUTPUT • • ANALOG INPUT AMP PIPELINED ADC SHIFT LATCHES • A – D0 IN REGISTER CLKOUT OGND SENSE BUFFER VDD 5V RANGE 1µF 1µF SELECT DIFF AMP 1µF VCM GND 2.35VREF CONTROL LOGIC 4.7µF 1741 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV OE 4.7µF 0.1µF 0.1µF DIFFERENTIAL 1µF 1µF ENCODE INPUT 1741f 1