LTC1742 WWWUUWUABSOLUTE MAXIMUM RATINGSPACKAGE/ORDER INFORMATIONOVDD = VDD (Notes 1, 2) ORDER PART Supply Voltage (VDD) ... 5.5V TOP VIEW NUMBER Analog Input Voltage (Note 3) .. – 0.3V to (VDD + 0.3V) SENSE 1 48 OF V 2 47 OGND Digital Input Voltage (Except OE) CM GND 3 46 D13 LTC1742CFW + (Note 3) .. – 0.3V to (V A 4 45 IN D12 DD + 0.3V) – LTC1742IFW A 5 44 IN D11 OE Input Voltage (Note 4) .. – 0.3V to (OVDD + 0.3V) GND 6 43 OVDD V 7 42 D10 Digital Output Voltage ... – 0.3V to (V DD DD + 0.3V) V 8 41 DD D9 OGND Voltage .. – 0.3V to 1V GND 9 40 D8 REFLB 10 39 D7 Power Dissipation .. 2000mW REFHA 11 38 OGND Operating Temperature Range GND 12 37 GND GND 13 36 GND LTC1742C ... 0°C to 70°C REFLA 14 35 D6 REFHB 15 34 D5 LTC1742I .. – 40°C to 85°C GND 16 33 D4 Storage Temperature Range ... – 65°C to 150°C V 17 32 DD OVDD V 18 31 DD D3 Lead Temperature (Soldering, 10 sec).. 300°C GND 19 30 D2 V 20 29 DD D1 GND 21 28 D0 MSBINV 22 27 OGND ENC 23 26 CLKOUT ENC 24 25 OE FW PACKAGE 48-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 35°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. UCO VERTER CHARACTERISTICS The ● indicates specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25 ° C. (Note 5)PARAMETERCONDITIONSMINTYPMAXUNITS Resolution (No Missing Codes) ● 14 Bits Integral Linearity Error (Note 6) – 3 ±0.75 3 LSB Differential Linearity Error ● –1 ±0.5 1 LSB Offset Error (Note 7) – 35 ±5 35 mV Gain Error External Reference (SENSE = 1.6V) – 3.5 ±1 3.5 %FS Full-Scale Drift Internal Reference ±40 ppm/°C Full-Scale Drift External Reference (SENSE = 1.6V) ±20 ppm/°C Offset Drift Internal Reference ±20 µV/°C Input Referred Noise (Transition Noise) SENSE = 1.6V 0.82 LSBRMS UUA ALOG I PUT The ● indicates specifications which apply over the full operating temperature range, otherwisespecifications are at TA = 25 ° C. (Note 5)SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS VIN Analog Input Range (Note 8) 4.75V ≤ VDD ≤ 5.25V ● ±1 to ±1.6 V I + – IN Analog Input Leakage Current 0 < AIN , AIN < VDD ● –1 1 µA CIN Analog Input Capacitance Sample Mode ENC < ENC 8 pF Hold Mode ENC > ENC 4 pF tACQ Sample-and-Hold Acquisition Time ● 5 7.3 ns tAP Sample-and-Hold Acquisition Delay Time 0 ns tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.15 psRMS CMRR Analog Input Common Mode Rejection Ratio 1.5V < (A – + IN = AIN ) < 3V 80 dB 1742f 2