Datasheet LTC1750 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 80Msps Wide Bandwidth ADC |
| 页数 / 页 | 20 / 9 — PI FU CTIO S. SENSE (Pin 1):. MSBINV (Pin 22):. ENC (Pin 23):. VCM (Pin … |
| 文件格式/大小 | PDF / 288 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. SENSE (Pin 1):. MSBINV (Pin 22):. ENC (Pin 23):. VCM (Pin 2):. ENC (Pin 24):
该数据表的模型线
文件文字版本
LTC1750
U U U PI FU CTIO S SENSE (Pin 1):
Reference Sense Pin. GND selects a VREF
MSBINV (Pin 22):
MSB Inversion Control. Low inverts the of 0.7V. VDD selects 1.125V. When VSENSE is between 0.7V MSB, 2’s complement output format. High does not invert and 1.125V, VSENSE is used as VREF. The ADC input range the MSB, offset binary output format. is ±VREF/PGA gain.
ENC (Pin 23):
Encode Input. The input sample starts on the
VCM (Pin 2):
2.0V Output and Input Common Mode Bias. positive edge. Bypass to ground with 4.7µF ceramic chip capacitor.
ENC (Pin 24):
Encode Complement Input. Conversion
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37):
ADC Power starts on the negative edge. Bypass to ground with 0.1µF Ground. ceramic for single-ended ENCODE signal.
A + IN (Pin 4):
Positive Differential Analog Input.
PGA (Pin 25):
Programmable Gain Amplifier Control. Low
A –
selects an effective front-end gain of 1. High selects an
IN (Pin 5):
Negative Differential Analog Input. effective gain of 1 2/3. The ADC input range is ±V
V
REF/PGA
DD (Pins 7, 8, 17, 18, 20):
5V Supply. Bypass to AGND gain. with 1µF ceramic chip capacitors at Pin 8 and Pin 18.
CLKOUT (Pin 26):
Data Valid Output. Latch data on the
REFLB (Pin 10):
ADC Low Reference. Bypass to Pin 11 rising edge of CLKOUT. with 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 14.
OGND (Pins 27, 38, 47):
Output Driver Ground.
REFHA (Pin 11):
ADC High Reference. Bypass to Pin 10 with
D0-D3 (Pins 28 to 31):
Digital Outputs. 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic
OVDD (Pins 32, 43):
Positive Supply for the Output Driv- capacitor and to ground with 1µF ceramic capacitor. ers. Bypass to ground with 0.1µF ceramic chip capacitor.
REFLA (Pin 14):
ADC Low Reference. Bypass to Pin 15 with
D4-D6 (Pins 33 to 35):
Digital Outputs. 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ce-
D7-D10 (Pins 39 to 42):
Digital Outputs. ramic capacitor and to ground with 1µF ceramic capacitor.
D11-D13 (Pins 44 to 46):
Digital Outputs.
REFHB (Pin 15):
ADC High Reference. Bypass to Pin 14
OF (Pin 48):
Over/Under Flow Output. High when an over with 0.1µF ceramic chip capacitor. Do not connect to or under flow has occurred. Pin␣ 11. 1750f 9
U U U PI FU CTIO S SENSE (Pin 1):
Reference Sense Pin. GND selects a VREF
MSBINV (Pin 22):
MSB Inversion Control. Low inverts the of 0.7V. VDD selects 1.125V. When VSENSE is between 0.7V MSB, 2’s complement output format. High does not invert and 1.125V, VSENSE is used as VREF. The ADC input range the MSB, offset binary output format. is ±VREF/PGA gain.
ENC (Pin 23):
Encode Input. The input sample starts on the
VCM (Pin 2):
2.0V Output and Input Common Mode Bias. positive edge. Bypass to ground with 4.7µF ceramic chip capacitor.
ENC (Pin 24):
Encode Complement Input. Conversion
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37):
ADC Power starts on the negative edge. Bypass to ground with 0.1µF Ground. ceramic for single-ended ENCODE signal.
A + IN (Pin 4):
Positive Differential Analog Input.
PGA (Pin 25):
Programmable Gain Amplifier Control. Low
A –
selects an effective front-end gain of 1. High selects an
IN (Pin 5):
Negative Differential Analog Input. effective gain of 1 2/3. The ADC input range is ±V
V
REF/PGA
DD (Pins 7, 8, 17, 18, 20):
5V Supply. Bypass to AGND gain. with 1µF ceramic chip capacitors at Pin 8 and Pin 18.
CLKOUT (Pin 26):
Data Valid Output. Latch data on the
REFLB (Pin 10):
ADC Low Reference. Bypass to Pin 11 rising edge of CLKOUT. with 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 14.
OGND (Pins 27, 38, 47):
Output Driver Ground.
REFHA (Pin 11):
ADC High Reference. Bypass to Pin 10 with
D0-D3 (Pins 28 to 31):
Digital Outputs. 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic
OVDD (Pins 32, 43):
Positive Supply for the Output Driv- capacitor and to ground with 1µF ceramic capacitor. ers. Bypass to ground with 0.1µF ceramic chip capacitor.
REFLA (Pin 14):
ADC Low Reference. Bypass to Pin 15 with
D4-D6 (Pins 33 to 35):
Digital Outputs. 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ce-
D7-D10 (Pins 39 to 42):
Digital Outputs. ramic capacitor and to ground with 1µF ceramic capacitor.
D11-D13 (Pins 44 to 46):
Digital Outputs.
REFHB (Pin 15):
ADC High Reference. Bypass to Pin 14
OF (Pin 48):
Over/Under Flow Output. High when an over with 0.1µF ceramic chip capacitor. Do not connect to or under flow has occurred. Pin␣ 11. 1750f 9