Datasheet LTC1854, LTC1855, LTC1856 (Analog Devices) - 5

LTC1854/LTC1855/LTC1856
Timing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency Through CH0 to CH7 Inputs l 100 kHz Through ADC+, ADC– Only 166 kHz tCONV Conversion Time l 4 5 µs tACQ Acquisition Time Through CH0 to CH7 Inputs l 4 µs Through ADC+, ADC– Only 1 µs fSCK SCK Frequency (Note 13) l 0 20 MHz tr SDO Rise Time See Test Circuits 6 ns tf SDO Fall Time See Test Circuits 6 ns t1 CONVST High Time l 40 ns t2 CONVST to BUSY Delay CL = 25pF, See Test Circuits l 15 30 ns t3 SCK Period l 50 ns t4 SCK High l 10 ns t5 SCK Low l 10 ns t6 Delay Time, SCK↓ to SDO Valid CL = 25pF, See Test Circuits l 25 45 ns t7 Time from Previous SDO Data Remains CL = 25pF, See Test Circuits l 5 20 ns Valid After SCK↓ t8 SDO Valid After RD↓ CL = 25pF, See Test Circuits l 11 30 ns t9 RD↓ to SCK Setup Time l 20 ns t10 SDI Setup Time Before SCK↑ l 0 ns t11 SDI Hold Time After SCK↑ l 7 ns t12 SDO Valid Before BUSY↑ RD = Low, CL = 25pF, See Test Circuits l 5 20 ns t13 Bus Relinquish Time See Test Circuits l 10 30 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual end points of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 8:
Bipolar zero error is the offset voltage measured from –0.5LSB
Note 2:
All voltage values are with respect to ground with DGND, AGND1, when the output code flickers between 0000 0000 0000 0000 and 1111 AGND2 and AGND3 wired together unless otherwise noted. 1111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 11
Note 3:
When these pin voltages are taken below ground or above AV 1111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 1111 DD = DV 1111 1111 for the LTC1854. DD = OVDD = VDD, they will be clamped by internal diodes. This product can handle currents of greater than 100mA below ground or above VDD
Note 9:
Guaranteed by design, not subject to test. without latchup.
Note 10:
Recommended operating conditions.
Note 4:
When these pin voltages are taken below ground they will be
Note 11:
Full-scale bipolar error is the worst case of –FS or +FS clamped by internal diodes. This product can handle currents of greater untrimmed deviation from ideal first and last code transitions, divided by than 100mA below ground without latchup. These pins are not clamped to the full-scale range, and includes the effect of offset error. VDD.
Note 12:
Recovers to specified performance after (2 • FS) input
Note 5:
VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise overvoltage. specified.
Note 13:
t6 of 45ns maximum allows fSCK up to 10MHz for rising capture
Note 6:
Linearity, offset and full-scale specifications apply for a single- with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns ended analog MUX input with respect to ground or ADC+ with respect to setup time for the receiving logic). ADC– tied to ground. 1854565af 5 Document Outline Description Typical Application Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Applications Information Package Description Typical Application Related Parts