Datasheet LTC1857, LTC1858, LTC1859 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 8-Channel, 16-Bit, 100ksps SoftSpan A/D Converters with Shutdown |
| 页数 / 页 | 22 / 5 — TIMING CHARACTERISTICS. The. denotes the specifications which apply over … |
| 文件格式/大小 | PDF / 393 Kb |
| 文件语言 | 英语 |
TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating temperature
该数据表的模型线
- LTC1857CG#PBF LTC1857CG#PBF LTC1857CG#TRPBF LTC1857CG#TRPBF LTC1857IG#PBF LTC1857IG#PBF LTC1857IG#TRPBF LTC1857IG#TRPBF
文件文字版本
LTC1857/LTC1858/LTC1859
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency Through CH0 to CH7 Inputs l 100 kHz Through ADC+, ADC– Only 166 kHz tCONV Conversion Time l 4 5 µs tACQ Acquisition Time Through CH0 to CH7 Inputs l 4 µs Through ADC+, ADC– Only 1 µs fSCK SCK Frequency (Note 14) l 0 20 MHz tr SDO Rise Time See Test Circuits 6 ns tf SDO Fall Time See Test Circuits 6 ns t1 CONVST High Time l 40 ns t2 CONVST to BUSY Delay CL = 25pF, See Test Circuits l 15 30 ns t3 SCK Period l 50 ns t4 SCK High l 10 ns t5 SCK Low l 10 ns t6 Delay Time, SCK↓ to SDO Valid CL = 25pF, See Test Circuits l 25 45 ns t7 Time from Previous SDO Data Remains CL = 25pF, See Test Circuits l 5 20 ns Valid After SCK↓ t8 SDO Valid After RD↓ CL = 25pF, See Test Circuits l 11 30 ns t9 RD↓ to SCK Setup Time l 20 ns t10 SDI Setup Time Before SCK↑ l 0 ns t11 SDI Hold Time After SCK↑ l 7 ns t12 SDO Valid Before BUSY↑ RD = Low, CL = 25pF, See Test Circuits l 5 20 ns t13 Bus Relinquish Time See Test Circuits l 10 30 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
Bipolar zero error is the offset voltage measured from –0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code flickers between 0000 0000 0000 0000 and 1111 Maximum Rating condition for extended periods may affect device 1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11 reliability and lifetime. 1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and
Note 2:
All voltage values are with respect to ground with DGND, AGND1, 1111 1111 1111 for the LTC1857. Unipolar zero error is the offset voltage AGND2 and AGND3 wired together unless otherwise noted. measured from 0.5LSB when the output codes flicker between 0000 0000
Note 3:
When these pin voltages are taken below ground or above AV 0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000 DD = DV 0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000 DD = OVDD = VDD, they will be clamped by internal diodes. This product can handle currents of greater than 100mA below ground or above V 0000 0000 and 0000 0000 0001 for the LTC1857. DD without latchup.
Note 9:
Guaranteed by design, not subject to test.
Note 4:
When these pin voltages are taken below ground they will be
Note 10:
Recommended operating conditions. clamped by internal diodes. This product can handle currents of greater
Note 11:
Full-scale bipolar error is the worst case of –FS or +FS than 100mA below ground without latchup. These pins are not clamped untrimmed deviation from ideal first and last code transitions, divided by to VDD. the full-scale range, and includes the effect of offset error. For unipolar
Note 5:
V full-scale error, the deviation of the last code transition from ideal, divided DD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise specified. by the full-scale range, and includes the effect of offset error.
Note 6:
Linearity, offset and full-scale specifications apply for a single-
Note 12:
All Specifications in dB are referred to a full-scale ±10V input. ended analog MUX input with respect to ground or ADC+ with respect to
Note 13:
Recovers to specified performance after (2 • FS) input ADC– tied to ground. overvoltage.
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
Note 14:
t6 of 45ns maximum allows fSCK up to 10MHz for rising capture straight line passing through the actual end points of the transfer curve. with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns The deviation is measured from the center of the quantization band. setup time for the receiving logic).
Note 15:
The specification is referred to the ±10V input range. 185789fb For more information www.linear.com/LTC1857 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter and Multplexer Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Test Circuits Timing Diagrams Operation Applications Information Package Description Revision History Typical Application Related Parts
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency Through CH0 to CH7 Inputs l 100 kHz Through ADC+, ADC– Only 166 kHz tCONV Conversion Time l 4 5 µs tACQ Acquisition Time Through CH0 to CH7 Inputs l 4 µs Through ADC+, ADC– Only 1 µs fSCK SCK Frequency (Note 14) l 0 20 MHz tr SDO Rise Time See Test Circuits 6 ns tf SDO Fall Time See Test Circuits 6 ns t1 CONVST High Time l 40 ns t2 CONVST to BUSY Delay CL = 25pF, See Test Circuits l 15 30 ns t3 SCK Period l 50 ns t4 SCK High l 10 ns t5 SCK Low l 10 ns t6 Delay Time, SCK↓ to SDO Valid CL = 25pF, See Test Circuits l 25 45 ns t7 Time from Previous SDO Data Remains CL = 25pF, See Test Circuits l 5 20 ns Valid After SCK↓ t8 SDO Valid After RD↓ CL = 25pF, See Test Circuits l 11 30 ns t9 RD↓ to SCK Setup Time l 20 ns t10 SDI Setup Time Before SCK↑ l 0 ns t11 SDI Hold Time After SCK↑ l 7 ns t12 SDO Valid Before BUSY↑ RD = Low, CL = 25pF, See Test Circuits l 5 20 ns t13 Bus Relinquish Time See Test Circuits l 10 30 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
Bipolar zero error is the offset voltage measured from –0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code flickers between 0000 0000 0000 0000 and 1111 Maximum Rating condition for extended periods may affect device 1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11 reliability and lifetime. 1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and
Note 2:
All voltage values are with respect to ground with DGND, AGND1, 1111 1111 1111 for the LTC1857. Unipolar zero error is the offset voltage AGND2 and AGND3 wired together unless otherwise noted. measured from 0.5LSB when the output codes flicker between 0000 0000
Note 3:
When these pin voltages are taken below ground or above AV 0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000 DD = DV 0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000 DD = OVDD = VDD, they will be clamped by internal diodes. This product can handle currents of greater than 100mA below ground or above V 0000 0000 and 0000 0000 0001 for the LTC1857. DD without latchup.
Note 9:
Guaranteed by design, not subject to test.
Note 4:
When these pin voltages are taken below ground they will be
Note 10:
Recommended operating conditions. clamped by internal diodes. This product can handle currents of greater
Note 11:
Full-scale bipolar error is the worst case of –FS or +FS than 100mA below ground without latchup. These pins are not clamped untrimmed deviation from ideal first and last code transitions, divided by to VDD. the full-scale range, and includes the effect of offset error. For unipolar
Note 5:
V full-scale error, the deviation of the last code transition from ideal, divided DD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise specified. by the full-scale range, and includes the effect of offset error.
Note 6:
Linearity, offset and full-scale specifications apply for a single-
Note 12:
All Specifications in dB are referred to a full-scale ±10V input. ended analog MUX input with respect to ground or ADC+ with respect to
Note 13:
Recovers to specified performance after (2 • FS) input ADC– tied to ground. overvoltage.
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
Note 14:
t6 of 45ns maximum allows fSCK up to 10MHz for rising capture straight line passing through the actual end points of the transfer curve. with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns The deviation is measured from the center of the quantization band. setup time for the receiving logic).
Note 15:
The specification is referred to the ±10V input range. 185789fb For more information www.linear.com/LTC1857 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter and Multplexer Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Test Circuits Timing Diagrams Operation Applications Information Package Description Revision History Typical Application Related Parts