Datasheet LTC1860L, LTC1861L (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | µPower, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP |
| 页数 / 页 | 12 / 10 — APPLICATIO S I FOR ATIO. Figure 4. LTC1861L Operating Sequence. Table 1. … |
| 文件格式/大小 | PDF / 240 Kb |
| 文件语言 | 英语 |
APPLICATIO S I FOR ATIO. Figure 4. LTC1861L Operating Sequence. Table 1. Multiplexer Channel Selection. MUX ADDRESS. CHANNEL #
该数据表的模型线
文件文字版本
LTC1860L/LTC1861L
U U W U APPLICATIO S I FOR ATIO
CONV tSMPL tCONV SLEEP MODE SDI DON’T CARE S/D O/S DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 SCK DON'T CARE SDO B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1860 F04
Figure 4. LTC1861L Operating Sequence
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Table 1. Multiplexer Channel Selection
•
MUX ADDRESS CHANNEL #
• •
SGL/DIFF ODD/SIGN 0 1 GND
0 0 0 0 0 0 0 0 0 0 0 1 V * SINGLE-ENDED 1 0 + – IN 0 0 0 0 0 0 0 0 0 0 0 0 MUX MODE 1 1 + – 0V 1LSB V V V CC CC CC – 2LSB – 1LSB DIFFERENTIAL 0 0 + – *V MUX MODE 0 1 – + IN = (SELECTED “+” CHANNEL) – (SELECTED “–” CHANNEL) 1860 F05 186465 TBL1 REFER TO TABLE 1
Figure 5. LTC1861L Transfer Curve GENERAL ANALOG CONSIDERATIONS
induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a
Grounding
minimum of 1µF tantalum. Keep the bypass capacitor The LTC1860L/LTC1861L should be used with an analog leads as short as possible. ground plane and single point grounding techniques. Do
Analog Inputs
not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, Because of the capacitive redistribution A/D conversion use a printed circuit board. The ground pins (AGND and techniques used, the analog inputs of the LTC1860L/ DGND for the LTC1861L MSOP package and GND for the LTC1861L have capacitive switching input current spikes. LTC1860L and LTC1861L SO-8 package) should be tied These current spikes settle quickly and do not cause a directly to the analog ground plane with minimum lead problem if source resistances are less than 200Ω or high length. speed op amps are used (e.g., the LT®1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large
Bypassing
source resistances are used, or if slow settling op amps For good performance, the V drive the inputs, take care to ensure the transients caused CC and VREF pins must be free of noise and ripple. Any changes in the V by the current spikes settle completely before the conver- CC/VREF voltage with respect to ground during the conversion cycle can sion begins. 18601Lf 10
U U W U APPLICATIO S I FOR ATIO
CONV tSMPL tCONV SLEEP MODE SDI DON’T CARE S/D O/S DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 SCK DON'T CARE SDO B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1860 F04
Figure 4. LTC1861L Operating Sequence
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Table 1. Multiplexer Channel Selection
•
MUX ADDRESS CHANNEL #
• •
SGL/DIFF ODD/SIGN 0 1 GND
0 0 0 0 0 0 0 0 0 0 0 1 V * SINGLE-ENDED 1 0 + – IN 0 0 0 0 0 0 0 0 0 0 0 0 MUX MODE 1 1 + – 0V 1LSB V V V CC CC CC – 2LSB – 1LSB DIFFERENTIAL 0 0 + – *V MUX MODE 0 1 – + IN = (SELECTED “+” CHANNEL) – (SELECTED “–” CHANNEL) 1860 F05 186465 TBL1 REFER TO TABLE 1
Figure 5. LTC1861L Transfer Curve GENERAL ANALOG CONSIDERATIONS
induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a
Grounding
minimum of 1µF tantalum. Keep the bypass capacitor The LTC1860L/LTC1861L should be used with an analog leads as short as possible. ground plane and single point grounding techniques. Do
Analog Inputs
not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, Because of the capacitive redistribution A/D conversion use a printed circuit board. The ground pins (AGND and techniques used, the analog inputs of the LTC1860L/ DGND for the LTC1861L MSOP package and GND for the LTC1861L have capacitive switching input current spikes. LTC1860L and LTC1861L SO-8 package) should be tied These current spikes settle quickly and do not cause a directly to the analog ground plane with minimum lead problem if source resistances are less than 200Ω or high length. speed op amps are used (e.g., the LT®1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large
Bypassing
source resistances are used, or if slow settling op amps For good performance, the V drive the inputs, take care to ensure the transients caused CC and VREF pins must be free of noise and ripple. Any changes in the V by the current spikes settle completely before the conver- CC/VREF voltage with respect to ground during the conversion cycle can sion begins. 18601Lf 10