Datasheet LTC2107 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 210Msps High Performance ADC |
| 页数 / 页 | 32 / 6 — p ower requirements The. denotes the specifications which apply over the … |
| 文件格式/大小 | PDF / 514 Kb |
| 文件语言 | 英语 |
p ower requirements The. denotes the specifications which apply over the full operating temperature
该数据表的模型线
文件文字版本
LTC2107
p ower requirements The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 9) l 2.375 2.5 2.625 V OVDD Output Supply Voltage CMOS Mode (Note 9) l 1.7 1.8 1.9 V LVDS Mode (Note 9) l 1.7 1.8 1.9 V IVDD Analog Supply Current l 495.3 545 mA IOVDD Digital Supply Current CMOS Mode 61 mA LVDS Mode, 1.75mA Mode l 23.2 26 mA LVDS Mode, 3.5mA Mode l 45 50 mA PDISS Power Dissipation CMOS Mode 1348 mW LVDS Mode, 1.75mA Mode l 1280 1409 mW LVDS Mode, 3.5mA Mode l 1320 1453 mW PSHDN SHDN Mode Power 6.4 mW IVDD Analog Supply Current with Inactive Encode Encode Clock Not Active 366 mA Keep Alive Oscillator Enabled
t iming characteristics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 9) l 10 210 MHz tL ENC Low Time Duty Cycle Stabilizer Off (Note 8) l 2.26 2.38 50 ns Duty Cycle Stabilizer On (Note 8) l 1.16 2.38 50 ns tH ENC High Time Duty Cycle Stabilizer Off (Note 8) l 2.26 2.38 50 ns Duty Cycle Stabilizer On (Note 8) l 1.16 2.38 50 ns tAP Sample-and-Hold Acquisition Delay Time RS = 25Ω 0.5 ns
Digital Data Outputs (CMOS Mode)
tD ENC to Data Delay CL = 6.8pF (Notes 8, 12) l 1.3 1.9 2.5 ns tC ENC to CLKOUT Delay CL = 6.8pF (Notes 8, 12) l 1.3 1.9 2.5 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l –0.3 0 0.3 ns Pipeline Latency 7 Cycles
Digital Data Outputs (LVDS Mode)
tD ENC to Data Delay CL = 6.8pF (Notes 8, 12) l 1.3 1.9 2.5 ns tC ENC to CLKOUT Delay CL = 6.8pF (Notes 8, 12) l 1.3 1.9 2.5 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l –0.3 0 0.3 ns Pipeline Latency 7 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Read Back Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tCSS CS Falling to SCK Rising Setup Time l 5 ns tSCH SCK Rising to CS Rising Hold Time l 5 ns tSCS SCK Falling to CS Falling Setup Time l 5 ns tDS SDI to SCK Rising Setup Time l 5 ns tDH SCK Rising to SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns 2107fb 6 For more information www.linear.com/LTC2107 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy VCM Output Digital Inputs and OUtputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Typical Application Related Parts
p ower requirements The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 9) l 2.375 2.5 2.625 V OVDD Output Supply Voltage CMOS Mode (Note 9) l 1.7 1.8 1.9 V LVDS Mode (Note 9) l 1.7 1.8 1.9 V IVDD Analog Supply Current l 495.3 545 mA IOVDD Digital Supply Current CMOS Mode 61 mA LVDS Mode, 1.75mA Mode l 23.2 26 mA LVDS Mode, 3.5mA Mode l 45 50 mA PDISS Power Dissipation CMOS Mode 1348 mW LVDS Mode, 1.75mA Mode l 1280 1409 mW LVDS Mode, 3.5mA Mode l 1320 1453 mW PSHDN SHDN Mode Power 6.4 mW IVDD Analog Supply Current with Inactive Encode Encode Clock Not Active 366 mA Keep Alive Oscillator Enabled
t iming characteristics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 9) l 10 210 MHz tL ENC Low Time Duty Cycle Stabilizer Off (Note 8) l 2.26 2.38 50 ns Duty Cycle Stabilizer On (Note 8) l 1.16 2.38 50 ns tH ENC High Time Duty Cycle Stabilizer Off (Note 8) l 2.26 2.38 50 ns Duty Cycle Stabilizer On (Note 8) l 1.16 2.38 50 ns tAP Sample-and-Hold Acquisition Delay Time RS = 25Ω 0.5 ns
Digital Data Outputs (CMOS Mode)
tD ENC to Data Delay CL = 6.8pF (Notes 8, 12) l 1.3 1.9 2.5 ns tC ENC to CLKOUT Delay CL = 6.8pF (Notes 8, 12) l 1.3 1.9 2.5 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l –0.3 0 0.3 ns Pipeline Latency 7 Cycles
Digital Data Outputs (LVDS Mode)
tD ENC to Data Delay CL = 6.8pF (Notes 8, 12) l 1.3 1.9 2.5 ns tC ENC to CLKOUT Delay CL = 6.8pF (Notes 8, 12) l 1.3 1.9 2.5 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l –0.3 0 0.3 ns Pipeline Latency 7 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Read Back Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tCSS CS Falling to SCK Rising Setup Time l 5 ns tSCH SCK Rising to CS Rising Hold Time l 5 ns tSCS SCK Falling to CS Falling Setup Time l 5 ns tDS SDI to SCK Rising Setup Time l 5 ns tDH SCK Rising to SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns 2107fb 6 For more information www.linear.com/LTC2107 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy VCM Output Digital Inputs and OUtputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Typical Application Related Parts