Datasheet LTC2123 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Dual 14-Bit 250Msps ADC with JESD204B Serial Outputs |
| 页数 / 页 | 50 / 5 — DIGITAL. INPUTS AND OUTPUTS The. denotes the specifications which apply … |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
DIGITAL. INPUTS AND OUTPUTS The. denotes the specifications which apply over the full operating
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LTC2123
DIGITAL INPUTS AND OUTPUTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CML Outputs
VDIFF CML Differential Output Voltage Output Current Set to 10mA 500 mVppd Output Current Set to 12mA 600 mVppd Output Current Set to 14mA 700 mVppd Output Current Set to 16mA 800 mVppd VOH Output High Level Directly-Coupled 50Ω to OVDD OVDD V Directly-Coupled 100Ω Differential OVDD–¼VDIFF V AC-Coupled OVDD–¼VDIFF V VOL Output Low Level Directly-Coupled 50Ω to OVDD OVDD–½VDIFF V Directly-Coupled 100Ω Differential OVDD–¾VDIFF V AC-Coupled OVDD–¾VDIFF V VOCM Output Common Mode Level Directly-Coupled 50Ω to OVDD OVDD–¼VDIFF V Directly-Coupled 100Ω Differential OVDD–½VDIFF V AC-Coupled OVDD–½VDIFF V ROUT Output Resistance Single-Ended 50 Ω Differential l 80 100 120 Ω
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS, 1/tS Sampling Frequency (Note 9) l 50 250 MHz tL 1× CLK Low Time (Note 8) Duty Cycle Stabilizer Off l 1.9 2 10 ns Duty Cycle Stabilizer On l 1.5 2 10 ns tH 1× CLK High Time (Note 8) Duty Cycle Stabilizer Off l 1.9 2 10 ns Duty Cycle Stabilizer On l 1.5 2 10 ns tDCK DEVCLK Period 2X_CLK SPI Register = 0 l 4 20 ns 2X_CLK SPI Register = 1 l 2 10 ns
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode CSDO = 20pF, RPULLUP = 2kΩ l 250 ns tCSS CS Falling to SCK Rising Set Up Time l 5 ns tSCH SCK Rising to CS Rising Hold Time l 5 ns tSCS SCK Falling to CS Falling Set Up Time l 5 ns tDS SDI to SCK Rising Set Up Time l 5 ns tDH SCK Rising to SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode CSDO = 20pF, RPULLUP = 2KΩ l 125 ns
JESD204B Timing (Note 8)
tBIT, UI High Speed Serial Bit Period 2 Lane Mode (1 Lane Per ADC) l 200 1000 ps 4 Lane Mode (2 Lanes Per ADC) l 400 1000 ps tJIT Total Jitter of CML Outputs (P-P) > 3.125Gbps Per Lane (BER = 1E-15, Note 8) l 0.3 UI ≤ 3.125Gbps Per Lane (BER = 1E-12, Note 8) l 0.35 UI 2123fc For more information www.linear.com/LTC2123 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Converter Characteristics Pin Configuration Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs and Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions Applications Information Typical Applications Package Description Typical Application Related Parts
DIGITAL INPUTS AND OUTPUTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CML Outputs
VDIFF CML Differential Output Voltage Output Current Set to 10mA 500 mVppd Output Current Set to 12mA 600 mVppd Output Current Set to 14mA 700 mVppd Output Current Set to 16mA 800 mVppd VOH Output High Level Directly-Coupled 50Ω to OVDD OVDD V Directly-Coupled 100Ω Differential OVDD–¼VDIFF V AC-Coupled OVDD–¼VDIFF V VOL Output Low Level Directly-Coupled 50Ω to OVDD OVDD–½VDIFF V Directly-Coupled 100Ω Differential OVDD–¾VDIFF V AC-Coupled OVDD–¾VDIFF V VOCM Output Common Mode Level Directly-Coupled 50Ω to OVDD OVDD–¼VDIFF V Directly-Coupled 100Ω Differential OVDD–½VDIFF V AC-Coupled OVDD–½VDIFF V ROUT Output Resistance Single-Ended 50 Ω Differential l 80 100 120 Ω
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS, 1/tS Sampling Frequency (Note 9) l 50 250 MHz tL 1× CLK Low Time (Note 8) Duty Cycle Stabilizer Off l 1.9 2 10 ns Duty Cycle Stabilizer On l 1.5 2 10 ns tH 1× CLK High Time (Note 8) Duty Cycle Stabilizer Off l 1.9 2 10 ns Duty Cycle Stabilizer On l 1.5 2 10 ns tDCK DEVCLK Period 2X_CLK SPI Register = 0 l 4 20 ns 2X_CLK SPI Register = 1 l 2 10 ns
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode CSDO = 20pF, RPULLUP = 2kΩ l 250 ns tCSS CS Falling to SCK Rising Set Up Time l 5 ns tSCH SCK Rising to CS Rising Hold Time l 5 ns tSCS SCK Falling to CS Falling Set Up Time l 5 ns tDS SDI to SCK Rising Set Up Time l 5 ns tDH SCK Rising to SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode CSDO = 20pF, RPULLUP = 2KΩ l 125 ns
JESD204B Timing (Note 8)
tBIT, UI High Speed Serial Bit Period 2 Lane Mode (1 Lane Per ADC) l 200 1000 ps 4 Lane Mode (2 Lanes Per ADC) l 400 1000 ps tJIT Total Jitter of CML Outputs (P-P) > 3.125Gbps Per Lane (BER = 1E-15, Note 8) l 0.3 UI ≤ 3.125Gbps Per Lane (BER = 1E-12, Note 8) l 0.35 UI 2123fc For more information www.linear.com/LTC2123 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Converter Characteristics Pin Configuration Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs and Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions Applications Information Typical Applications Package Description Typical Application Related Parts