Datasheet LTC2142-12, LTC2141-12, LTC2140-12 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 65Msps Low Power Dual ADCs |
| 页数 / 页 | 38 / 4 — CONVERTER CHARACTERISTICS. The. denotes the specifications which apply … |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
CONVERTER CHARACTERISTICS. The. denotes the specifications which apply over the full operating
该数据表的模型线
- LTC2140CUP-12#PBF LTC2140CUP-12#PBF LTC2140CUP-12#TRPBF LTC2140CUP-12#TRPBF LTC2140IUP-12#PBF LTC2140IUP-12#PBF LTC2140IUP-12#TRPBF LTC2140IUP-12#TRPBF
文件文字版本
LTC2142-12/ LTC2141-12/LTC2140-12
CONVERTER CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2142-12 LTC2141-12 LTC2140-12 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Resolution (No Missing Codes) l 12 12 12 Bits Integral Linearity Error Differential Analog Input (Note 6) l –0.9 ±0.3 0.9 –0.9 ±0.3 0.9 –0.9 ±0.3 0.9 LSB Differential Linearity Error Differential Analog Input l –0.5 ±0.1 0.5 –0.5 ±0.1 0.5 –0.5 ±0.1 0.5 LSB Offset Error (Note 7) l –9 ±1.5 9 –9 ±1.5 9 –9 ±1.5 9 mV Gain Error Internal Reference ±1.5 ±1.5 ±1.5 %FS External Reference l –1.7 –0.3 1.1 –1.7 –0.3 1.1 –1.7 –0.3 1.1 %FS Offset Drift ±10 ±10 ±10 μV/°C Full-Scale Drift Internal Reference ±30 ±30 ±30 ppm/°C External Reference ±10 ±10 ±10 ppm/°C Gain Matching ±0.2 ±0.2 ±0.2 %FS Offset Matching ±1.5 ±1.5 ±1.5 mV Transition Noise 0.3 0.3 0.3 LSBRMS
ANALOG INPUT The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V + – IN Analog Input Range (AIN – AIN ) 1.7V < VDD < 1.9V l 1 to 2 VP-P V + – IN(CM) Analog Input Common Mode (AIN + AIN )/2 Differential Analog Input (Note 8) l 0.7 VCM 1.25 V VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 0.625 1.250 1.300 V IINCM Analog Input Common Mode Current Per Pin, 65Msps 81 μA Per Pin, 40Msps 50 μA Per Pin, 25Msps 31 μA I + – IN1 Analog Input Leakage Current (No Encode) 0 < AIN , AIN < VDD l –1.5 1.5 μA IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l –3 3 μA IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l –3 3 μA tAP Sample-and-Hold Acquisition Delay Time 0 ns tJITTER Sample-and-Hold Acquisition Delay Jitter Single-Ended Encode 0.08 psRMS Differential Encode 0.10 psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB BW-3B Full-Power Bandwidth Figure 6 Test Circuit 750 MHz 21421012fa 4
CONVERTER CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2142-12 LTC2141-12 LTC2140-12 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Resolution (No Missing Codes) l 12 12 12 Bits Integral Linearity Error Differential Analog Input (Note 6) l –0.9 ±0.3 0.9 –0.9 ±0.3 0.9 –0.9 ±0.3 0.9 LSB Differential Linearity Error Differential Analog Input l –0.5 ±0.1 0.5 –0.5 ±0.1 0.5 –0.5 ±0.1 0.5 LSB Offset Error (Note 7) l –9 ±1.5 9 –9 ±1.5 9 –9 ±1.5 9 mV Gain Error Internal Reference ±1.5 ±1.5 ±1.5 %FS External Reference l –1.7 –0.3 1.1 –1.7 –0.3 1.1 –1.7 –0.3 1.1 %FS Offset Drift ±10 ±10 ±10 μV/°C Full-Scale Drift Internal Reference ±30 ±30 ±30 ppm/°C External Reference ±10 ±10 ±10 ppm/°C Gain Matching ±0.2 ±0.2 ±0.2 %FS Offset Matching ±1.5 ±1.5 ±1.5 mV Transition Noise 0.3 0.3 0.3 LSBRMS
ANALOG INPUT The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V + – IN Analog Input Range (AIN – AIN ) 1.7V < VDD < 1.9V l 1 to 2 VP-P V + – IN(CM) Analog Input Common Mode (AIN + AIN )/2 Differential Analog Input (Note 8) l 0.7 VCM 1.25 V VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 0.625 1.250 1.300 V IINCM Analog Input Common Mode Current Per Pin, 65Msps 81 μA Per Pin, 40Msps 50 μA Per Pin, 25Msps 31 μA I + – IN1 Analog Input Leakage Current (No Encode) 0 < AIN , AIN < VDD l –1.5 1.5 μA IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l –3 3 μA IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l –3 3 μA tAP Sample-and-Hold Acquisition Delay Time 0 ns tJITTER Sample-and-Hold Acquisition Delay Jitter Single-Ended Encode 0.08 psRMS Differential Encode 0.10 psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB BW-3B Full-Power Bandwidth Figure 6 Test Circuit 750 MHz 21421012fa 4