Datasheet LTC2142-12, LTC2141-12, LTC2140-12 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 65Msps Low Power Dual ADCs |
| 页数 / 页 | 38 / 8 — TIMING CHARACTERISTICS. The. denotes the specifications which apply over … |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating temperature
该数据表的模型线
- LTC2140CUP-12#PBF LTC2140CUP-12#PBF LTC2140CUP-12#TRPBF LTC2140CUP-12#TRPBF LTC2140IUP-12#PBF LTC2140IUP-12#PBF LTC2140IUP-12#TRPBF LTC2140IUP-12#TRPBF
文件文字版本
LTC2142-12/ LTC2141-12/LTC2140-12
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (LVDS Mode)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 6.5 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when
Note 2:
All voltage values are with respect to GND with GND and OGND the output code flickers between 0000 0000 0000 and 1111 1111 1111 in shorted (unless otherwise noted). 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
VDD = 1.8V, fSAMPLE = 65MHz (LTC2142), 40MHz (LTC2141), or of greater than 100mA below GND or above VDD without latchup. 25MHz (LTC2140), CMOS outputs, ENC+ = single-ended 1.8V square
Note 4:
When these pin voltages are taken below GND they will be wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on clamped by internal diodes. When these pin voltages are taken above VDD each digital output unless otherwise noted. The supply current and power they will not be clamped by internal diodes. This product can handle input dissipation specifications are totals for the entire IC, not per channel. currents of greater than 100mA below GND without latchup.
Note 10:
Recommended operating conditions.
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2142), 40MHz (LTC2141), or 25MHz (LTC2140), LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. 21421012fa 8
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (LVDS Mode)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 6.5 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when
Note 2:
All voltage values are with respect to GND with GND and OGND the output code flickers between 0000 0000 0000 and 1111 1111 1111 in shorted (unless otherwise noted). 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
VDD = 1.8V, fSAMPLE = 65MHz (LTC2142), 40MHz (LTC2141), or of greater than 100mA below GND or above VDD without latchup. 25MHz (LTC2140), CMOS outputs, ENC+ = single-ended 1.8V square
Note 4:
When these pin voltages are taken below GND they will be wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on clamped by internal diodes. When these pin voltages are taken above VDD each digital output unless otherwise noted. The supply current and power they will not be clamped by internal diodes. This product can handle input dissipation specifications are totals for the entire IC, not per channel. currents of greater than 100mA below GND without latchup.
Note 10:
Recommended operating conditions.
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2142), 40MHz (LTC2141), or 25MHz (LTC2140), LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. 21421012fa 8