Datasheet LTC2157-14, LTC2156-14, LTC2155-14 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | Dual 14-Bit 250Msps ADCs |
| 页数 / 页 | 34 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2157-14 32K … |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2157-14 32K Point FFT,. fIN = 15MHz, –1dBFS, 250Msps
该数据表的模型线
- LTC2155CUP-14#PBF LTC2155CUP-14#PBF LTC2155CUP-14#TRPBF LTC2155CUP-14#TRPBF LTC2155IUP-14#PBF LTC2155IUP-14#PBF LTC2155IUP-14#TRPBF LTC2155IUP-14#TRPBF
文件文字版本
LTC2157-14/ LTC2156-14/LTC2155-14 Dual 14-Bit 250Msps/ 210Msps/170Msps ADCs
FEATURES DESCRIPTION
n 70dB SNR The LTC®2157-14/LTC2156-14/LTC2155-14 are 2-channel n 90dB SFDR simultaneous sampling 250Msps/210Msps/170Msps n Low Power: 650mW/616mW/567mW Total 14-bit A/D converters designed for digitizing high fre- n Single 1.8V Supply quency, wide dynamic range signals. They are perfect n DDR LVDS Outputs for demanding communications applications with AC n Easy-to-Drive 1.5VP-P Input Range performance that includes 70dB SNR and 90dB spurious n 1.25GHz Full Power Bandwidth S/H free dynamic range (SFDR). The 1.25GHz input bandwidth n Optional Clock Duty Cycle Stabilizer allows the ADC to undersample high frequencies with n Low Power Sleep and Nap Modes good performance. The latency is only six clock cycles. n Serial SPI Port for Configuration DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ) n Pin-Compatible 12-Bit Versions and no missing codes over temperature. The transition n 64-Pin (9mm × 9mm) QFN Package noise is 1.82LSBRMS.
APPLICATIONS
The digital outputs are double data rate (DDR) LVDS. n Communications The ENC+ and ENC– inputs can be driven differentially with n Cellular Basestations a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional n Software Defined Radios clock duty cycle stabilizer allows high performance at full n Medical Imaging speed for a wide range of clock duty cycles. n High Definition Video L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Testing and Measurement Instruments
TYPICAL APPLICATION LTC2157-14 32K Point FFT,
VDD
fIN = 15MHz, –1dBFS, 250Msps
OVDD CHANNEL A 0 DA12_13 14-BIT ANALOG CORRECTION • –20 S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • ADC CORE LVDS • DA0_1 –40 –60 CLOCK/DUTY OGND CLOCK CYCLE CONTROL OV –80 DD AMPLITUDE (dBFS) CHANNEL B –100 DB12_13 14-BIT • ANALOG CORRECTION –120 S/H OUTPUT PIPELINED • DDR INPUT LOGIC DRIVERS 0 20 40 60 80 100 120 ADC CORE • LVDS FREQUENCY (MHz) DB0_1 21576514 TA01b GND 21576514 TA01 OGND 21576514fb For more information www.linear.com/LTC2157-14 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Package Description Related Parts
FEATURES DESCRIPTION
n 70dB SNR The LTC®2157-14/LTC2156-14/LTC2155-14 are 2-channel n 90dB SFDR simultaneous sampling 250Msps/210Msps/170Msps n Low Power: 650mW/616mW/567mW Total 14-bit A/D converters designed for digitizing high fre- n Single 1.8V Supply quency, wide dynamic range signals. They are perfect n DDR LVDS Outputs for demanding communications applications with AC n Easy-to-Drive 1.5VP-P Input Range performance that includes 70dB SNR and 90dB spurious n 1.25GHz Full Power Bandwidth S/H free dynamic range (SFDR). The 1.25GHz input bandwidth n Optional Clock Duty Cycle Stabilizer allows the ADC to undersample high frequencies with n Low Power Sleep and Nap Modes good performance. The latency is only six clock cycles. n Serial SPI Port for Configuration DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ) n Pin-Compatible 12-Bit Versions and no missing codes over temperature. The transition n 64-Pin (9mm × 9mm) QFN Package noise is 1.82LSBRMS.
APPLICATIONS
The digital outputs are double data rate (DDR) LVDS. n Communications The ENC+ and ENC– inputs can be driven differentially with n Cellular Basestations a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional n Software Defined Radios clock duty cycle stabilizer allows high performance at full n Medical Imaging speed for a wide range of clock duty cycles. n High Definition Video L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Testing and Measurement Instruments
TYPICAL APPLICATION LTC2157-14 32K Point FFT,
VDD
fIN = 15MHz, –1dBFS, 250Msps
OVDD CHANNEL A 0 DA12_13 14-BIT ANALOG CORRECTION • –20 S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • ADC CORE LVDS • DA0_1 –40 –60 CLOCK/DUTY OGND CLOCK CYCLE CONTROL OV –80 DD AMPLITUDE (dBFS) CHANNEL B –100 DB12_13 14-BIT • ANALOG CORRECTION –120 S/H OUTPUT PIPELINED • DDR INPUT LOGIC DRIVERS 0 20 40 60 80 100 120 ADC CORE • LVDS FREQUENCY (MHz) DB0_1 21576514 TA01b GND 21576514 TA01 OGND 21576514fb For more information www.linear.com/LTC2157-14 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Package Description Related Parts