Datasheet LTC2158-12 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | Dual 12-Bit 310Msps ADC |
| 页数 / 页 | 28 / 9 — PIN FUNCTIONS SDI (Pin 60):. LVDS Outputs. OF–/OF+ (Pins 22/23):. SCK … |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
PIN FUNCTIONS SDI (Pin 60):. LVDS Outputs. OF–/OF+ (Pins 22/23):. SCK (Pin 61):
该数据表的模型线
文件文字版本
LTC2158-12
PIN FUNCTIONS SDI (Pin 60):
Serial Interface Data Input. In serial program-
LVDS Outputs
ming mode, (PAR/SER = 0V), SDI is the serial interface The following pins are differential LVDS outputs. The data input. Data on SDI is clocked into the mode control output current level is programmable. There is an optional registers on the rising edge of SCK. In the parallel pro- internal 100Ω termination resistor between the pins of gramming mode (PAR/SER = VDD), SDI selects 3.5mA or each LVDS output pair. 1.75mA LVDS output current (see Table 2). SDI can be driven with 1.8V to 3.3V logic.
OF–/OF+ (Pins 22/23):
Over/Underflow Digital Output. OF+ is high when an overflow or underflow has occurred.
SCK (Pin 61):
Serial Interface Clock Input. In serial The overflows for channel A and channel B are multiplexed programming mode, (PAR/SER = 0V), SCK is the serial together. interface clock input. In the parallel programming mode (PAR/SER = V
– + – +
DD), SCK can be used to place the part in the
DB0_1 /DB0_1 to DB10_11 /DB10_11 (Pins 26/27, 28/29,
low power sleep mode (see Table 2). SCK can be driven
30/31, 34/35, 36/37, 38/39):
Channel B Double Data Rate with 1.8V to 3.3V logic. Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (DB0, DB2, DB4,
CS (Pin 62):
Serial Interface Chip Select Input. In serial DB6, DB8, DB10) appear when CLKOUT+ is low. The odd programming mode, (PAR/SER = 0V), CS is the serial in- data bits (DB1, DB3, DB5, DB7, DB9, DB11) appear when terface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. CLKOUT+ is high. In the parallel programming mode (PAR/SER = VDD), CS
CLKOUT–/CLKOUT+ (Pins 40/41):
Data Output Clock. controls the clock duty cycle stabilizer (see Table 2). CS The digital outputs normally transition at the same time can be driven with 1.8V to 3.3V logic. as the falling and rising edges of CLKOUT+. The phase of
PAR/SER (Pin 63):
Programming Mode Selection Pin. CLKOUT+ can also be delayed relative to the digital outputs Connect to ground to enable the serial programming mode by programming the mode control registers. where CS, SCK, SDI, SDO become a serial interface that
D – + – + A0_1 /DA0_1 to DA10_11 /DA10_11 (Pins 44/45, 46/47,
control the A/D operating modes. Connect to VDD to en-
50/51, 52/53, 54/55, 56/57):
Channel A Double Data Rate able the parallel programming mode where CS, SCK, SDI Digital Outputs. Two data bits are multiplexed onto each become parallel logic inputs that control a reduced set of differential output pair. The even data bits (DA0, DA2, DA4, the A/D operating modes. PAR/SER should be connected DA6, DA8, DA10) appear when CLKOUT+ is low. The odd directly to ground or the VDD of the part and not be driven data bits (DA1, DA3, DA5, DA7, DA9, DA11) appear when by a logic signal. CLKOUT+ is high. 215812fa For more information www.linear.com/LTC2158-12 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Related Parts
PIN FUNCTIONS SDI (Pin 60):
Serial Interface Data Input. In serial program-
LVDS Outputs
ming mode, (PAR/SER = 0V), SDI is the serial interface The following pins are differential LVDS outputs. The data input. Data on SDI is clocked into the mode control output current level is programmable. There is an optional registers on the rising edge of SCK. In the parallel pro- internal 100Ω termination resistor between the pins of gramming mode (PAR/SER = VDD), SDI selects 3.5mA or each LVDS output pair. 1.75mA LVDS output current (see Table 2). SDI can be driven with 1.8V to 3.3V logic.
OF–/OF+ (Pins 22/23):
Over/Underflow Digital Output. OF+ is high when an overflow or underflow has occurred.
SCK (Pin 61):
Serial Interface Clock Input. In serial The overflows for channel A and channel B are multiplexed programming mode, (PAR/SER = 0V), SCK is the serial together. interface clock input. In the parallel programming mode (PAR/SER = V
– + – +
DD), SCK can be used to place the part in the
DB0_1 /DB0_1 to DB10_11 /DB10_11 (Pins 26/27, 28/29,
low power sleep mode (see Table 2). SCK can be driven
30/31, 34/35, 36/37, 38/39):
Channel B Double Data Rate with 1.8V to 3.3V logic. Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (DB0, DB2, DB4,
CS (Pin 62):
Serial Interface Chip Select Input. In serial DB6, DB8, DB10) appear when CLKOUT+ is low. The odd programming mode, (PAR/SER = 0V), CS is the serial in- data bits (DB1, DB3, DB5, DB7, DB9, DB11) appear when terface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. CLKOUT+ is high. In the parallel programming mode (PAR/SER = VDD), CS
CLKOUT–/CLKOUT+ (Pins 40/41):
Data Output Clock. controls the clock duty cycle stabilizer (see Table 2). CS The digital outputs normally transition at the same time can be driven with 1.8V to 3.3V logic. as the falling and rising edges of CLKOUT+. The phase of
PAR/SER (Pin 63):
Programming Mode Selection Pin. CLKOUT+ can also be delayed relative to the digital outputs Connect to ground to enable the serial programming mode by programming the mode control registers. where CS, SCK, SDI, SDO become a serial interface that
D – + – + A0_1 /DA0_1 to DA10_11 /DA10_11 (Pins 44/45, 46/47,
control the A/D operating modes. Connect to VDD to en-
50/51, 52/53, 54/55, 56/57):
Channel A Double Data Rate able the parallel programming mode where CS, SCK, SDI Digital Outputs. Two data bits are multiplexed onto each become parallel logic inputs that control a reduced set of differential output pair. The even data bits (DA0, DA2, DA4, the A/D operating modes. PAR/SER should be connected DA6, DA8, DA10) appear when CLKOUT+ is low. The odd directly to ground or the VDD of the part and not be driven data bits (DA1, DA3, DA5, DA7, DA9, DA11) appear when by a logic signal. CLKOUT+ is high. 215812fa For more information www.linear.com/LTC2158-12 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Related Parts