Datasheet LTC2175-12, LTC2174-12, LTC2173-12 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 125Msps Low Power Quad ADCs |
| 页数 / 页 | 34 / 1 — FeaTures. DescripTion. 4-Channel Simultaneous Sampling ADC. 70.6dB SNR. … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
FeaTures. DescripTion. 4-Channel Simultaneous Sampling ADC. 70.6dB SNR. 88dB SFDR. applicaTions. Typical applicaTion
该数据表的模型线
- LTC2173CUKG-12#PBF LTC2173CUKG-12#PBF LTC2173CUKG-12#TRPBF LTC2173CUKG-12#TRPBF LTC2173IUKG-12#PBF LTC2173IUKG-12#PBF LTC2173IUKG-12#TRPBF LTC2173IUKG-12#TRPBF
文件文字版本
LTC2175-12/ LTC2174-12/LTC2173-12 12-Bit, 125Msps/105Msps/ 80Msps Low Power Quad ADCs
FeaTures DescripTion
n
4-Channel Simultaneous Sampling ADC
The LTC®2175-12/LTC2174-12/LTC2173-12 are 4-channel, n
70.6dB SNR
simultaneous sampling 12-bit A/D converters designed n
88dB SFDR
for digitizing high frequency, wide dynamic range signals. n Low Power: 545mW/439mW/369mW Total, They are perfect for demanding communications applica- 136mW/110mW/92mW per Channel tions with AC performance that includes 70.6dB SNR and n Single 1.8V Supply 88dB spurious free dynamic range (SFDR). Ultralow jitter n Serial LVDS Outputs: 1 or 2 Bits per Channel of 0.15psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1V excellent noise performance. P-P to 2VP-P n 800MHz Full Power Bandwidth S/H DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) n Shutdown and Nap Modes and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is a low 0.3LSBRMS. n Pin Compatible 14-Bit and 12-Bit Versions n The digital outputs are serial LVDS to minimize the num- 52-Pin (7mm × 8mm) QFN Package ber of data lines. Each channel outputs two bits at a time
applicaTions
(2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The LVDS drivers have n Communications optional internal termination and adjustable output levels n Cellular Base Stations to ensure clean signal integrity. n Software Defined Radios The ENC+ and ENC– inputs may be driven differentially n Portable Medical Imaging or single-ended with a sine wave, PECL, LVDS, TTL, or n Multichannel Data Acquisition CMOS inputs. An internal clock duty cycle stabilizer al- n Nondestructive Testing lows high performance at full speed for a wide range of L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. clock duty cycles.
Typical applicaTion
1.8V 1.8V
LTC2175-12, 125Msps,
VDD OVDD
2-Tone FFT, fIN = 70MHz and 75MHz
CHANNEL 1 12-BIT OUT1A 0 ANALOG S/H ADC CORE –10 INPUT OUT1B –20 CHANNEL 2 12-BIT OUT2A –30 ANALOG S/H ADC CORE INPUT OUT2B –40 DATA –50 SERIALIZER CHANNEL 3 SERIALIZED 12-BIT OUT3A –60 ANALOG S/H LVDS ADC CORE OUT3B INPUT OUTPUTS –70 AMPLITUDE (dBFS) –80 CHANNEL 4 OUT4A 12-BIT –90 ANALOG S/H ADC CORE OUT4B –100 INPUT –110 DATA CLOCK –120 ENCODE 0 PLL OUT 10 20 30 40 50 60 INPUT FREQUENCY (MHz) FRAME 217512 TA01b GND OGND 217512 TA01 21754312fa 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
FeaTures DescripTion
n
4-Channel Simultaneous Sampling ADC
The LTC®2175-12/LTC2174-12/LTC2173-12 are 4-channel, n
70.6dB SNR
simultaneous sampling 12-bit A/D converters designed n
88dB SFDR
for digitizing high frequency, wide dynamic range signals. n Low Power: 545mW/439mW/369mW Total, They are perfect for demanding communications applica- 136mW/110mW/92mW per Channel tions with AC performance that includes 70.6dB SNR and n Single 1.8V Supply 88dB spurious free dynamic range (SFDR). Ultralow jitter n Serial LVDS Outputs: 1 or 2 Bits per Channel of 0.15psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1V excellent noise performance. P-P to 2VP-P n 800MHz Full Power Bandwidth S/H DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) n Shutdown and Nap Modes and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is a low 0.3LSBRMS. n Pin Compatible 14-Bit and 12-Bit Versions n The digital outputs are serial LVDS to minimize the num- 52-Pin (7mm × 8mm) QFN Package ber of data lines. Each channel outputs two bits at a time
applicaTions
(2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The LVDS drivers have n Communications optional internal termination and adjustable output levels n Cellular Base Stations to ensure clean signal integrity. n Software Defined Radios The ENC+ and ENC– inputs may be driven differentially n Portable Medical Imaging or single-ended with a sine wave, PECL, LVDS, TTL, or n Multichannel Data Acquisition CMOS inputs. An internal clock duty cycle stabilizer al- n Nondestructive Testing lows high performance at full speed for a wide range of L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. clock duty cycles.
Typical applicaTion
1.8V 1.8V
LTC2175-12, 125Msps,
VDD OVDD
2-Tone FFT, fIN = 70MHz and 75MHz
CHANNEL 1 12-BIT OUT1A 0 ANALOG S/H ADC CORE –10 INPUT OUT1B –20 CHANNEL 2 12-BIT OUT2A –30 ANALOG S/H ADC CORE INPUT OUT2B –40 DATA –50 SERIALIZER CHANNEL 3 SERIALIZED 12-BIT OUT3A –60 ANALOG S/H LVDS ADC CORE OUT3B INPUT OUTPUTS –70 AMPLITUDE (dBFS) –80 CHANNEL 4 OUT4A 12-BIT –90 ANALOG S/H ADC CORE OUT4B –100 INPUT –110 DATA CLOCK –120 ENCODE 0 PLL OUT 10 20 30 40 50 60 INPUT FREQUENCY (MHz) FRAME 217512 TA01b GND OGND 217512 TA01 21754312fa 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts