Datasheet LTC2175-14, LTC2174-14, LTC2173-14 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 125Msps Low Power Quad ADCs |
| 页数 / 页 | 34 / 10 — TiMing DiagraMs. One-Lane Output Mode, 14-Bit Serialization. One-Lane … |
| 文件格式/大小 | PDF / 873 Kb |
| 文件语言 | 英语 |
TiMing DiagraMs. One-Lane Output Mode, 14-Bit Serialization. One-Lane Output Mode, 12-Bit Serialization
该数据表的模型线
- LTC2173CUKG-14#PBF LTC2173CUKG-14#PBF LTC2173CUKG-14#TRPBF LTC2173CUKG-14#TRPBF LTC2173IUKG-14#PBF LTC2173IUKG-14#PBF LTC2173IUKG-14#TRPBF LTC2173IUKG-14#TRPBF
文件文字版本
LTC2175-14/ LTC2174-14/LTC2173-14
TiMing DiagraMs One-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217514 TD06 OUT#B+, OUT#B– ARE DISABLED
One-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D5 D4 D3 D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217514 TD07 OUT#B+, OUT#B– ARE DISABLED
SPI Port Timing (Readback Mode)
tS tDS tDH tSCK tH CS SCK tDO SDI R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX SDO D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS SCK SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO 217514 TD04 HIGH IMPEDANCE 21754314fa 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TiMing DiagraMs One-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217514 TD06 OUT#B+, OUT#B– ARE DISABLED
One-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D5 D4 D3 D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217514 TD07 OUT#B+, OUT#B– ARE DISABLED
SPI Port Timing (Readback Mode)
tS tDS tDH tSCK tH CS SCK tDO SDI R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX SDO D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS SCK SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO 217514 TD04 HIGH IMPEDANCE 21754314fa 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts